DRV2624 Datasheet, PDF (20/79 Pages) Texas Instruments – DRV2624 Ultra Low Power Closed-Loop LRA/ERM Haptic Driver with Internal Memory

DRV2624
SLOS893A – DECEMBER 2015 – REVISED DECEMBER 2015
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8.4 Device Functional Modes
8.4.1 Power States
The DRV2624 device has multiple power states to optimize power consumption. In the event of a critical
condition, the DRV2624 device goes immediately into the standby state. Figure 22 shows the transitions into and
out of each state.
/ NRST = 0
/ NRST = 0
Shutdown
/ NRST = 1
Powering Up
/ NRST = 0
/ POR = 0
/ Finish Powering Up
/ POR = 0
/ NRST = 0
/ POR = 0
/ NRST = 0
Active
/ Waveform Triggered
/ I2C Transaction
Pseudo Standby
Standby
/ I2C Transaction Done
/ Waveform Triggered
/ Waveform Finished
/ Critical Condition
Figure 22. Power State Diagram
8.4.2 Operation With V_DD < 2.5 V (Minimum V_DD)
Operating the device with a V_DD value below 2.5 V is not recommended.
8.4.3 Operation With V_DD > 6 V (Absolute Maximum V_DD)
The DRV2624 device is designed to operate at up to 5.5 V with an absolute maximum voltage of 6 V . If exposed
to voltages above 6 V, the device can suffer permanent damage.
8.4.4 Operation in Shutdown State
The NRST pin of the DRV2624 device gates the power-up of the device. When NRST is asserted (logic low), all
internal blocks of the device (including I²C controller) are off to achieve ultra low power.
When the NRST pin is deaserted (logic high), the DRV2624 device powers-up, loads all the default conditions
and goes into standby state to preserve power.
Asserting the NRST pin has an immediate effect. Any process being executed will be aborted immediately and
the device will go into shutdown state.
The DRV2624 device allows for the NRST to be permanently tied directly to VDD, in which case the shutdown
state will be bypassed.
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