DDC232_15 Datasheet, PDF (20/34 Pages) Texas Instruments – 32-Channel, Current-Input Analog-to-Digital Converter

DDC232
SBAS331D – AUGUST 2004 – REVISED APRIL 2010
DATA FORMAT
The serial output data are provided in an offset binary
code as shown in Table 12. The Format bit in the
configuration register selects how many bits are used
in the output word. When Format = 1, 20 bits are
used. When Format = 0, the lower 4 bits are
truncated so that only 16 bits are used. Note that the
LSB size is 16 times bigger when Format = 0. An
offset is included in the output to allow slightly
negative inputs (for example, from board leakages)
from clipping the reading. This offset is approximately
0.4% of the positive full-scale.
BLANKSPACE
DATA RETRIEVAL
In both the Continuous and Noncontinuous modes of
operation, the data from the last conversion are
available for retrieval on the falling edge of DVALID
(see Figure 17 and Table 13). Data are shifted out on
the falling edge of the data clock, DCLK.
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Table 12. Ideal Output Code⁽¹⁾ vs Input Signal
INPUT
SIGNAL
≥ 100% FS
0.001531% FS
0.001436% FS
0.000191% FS
0.000096% FS
0% FS
–0.3955% FS
IDEAL OUTPUT CODE
FORMAT = 1
1111 1111 1111 1111 1111
0000 0001 0000 0001 0000
0000 0001 0000 0000 1111
0000 0001 0000 0000 0010
0000 0001 0000 0000 0001
0000 0001 0000 0000 0000
0000 0000 0000 0000 0000
IDEAL OUTPUT CODE
FORMAT = 0
1111 1111 1111 1111
0000 0001 0000 0001
0000 0001 0000 0000
0000 0001 0000 0000
0000 0001 0000 0000
0000 0001 0000 0000
0000 0000 0000 0000
(1) Excludes the effects of noise, INL, offset, and gain errors.
Make sure not to retrieve data around changes in
CONV because this can introduce noise. Stop activity
on DCLK at least 10ms before or after a CONV
transition.
Setting the Format bit = 0 (16-bit output word) will
reduce the time needed to retrieve data by 20% since
there are fewer bits to shift out. This can be useful in
multichannel systems requiring only 16 bits of
resolution.
CLK
DVALID
t_HDDODV
DCLK
t_PDCDV
t_PDDCDV
DOUT
Input 32
MSB
t_HDDODC
Input
32
LSB
Input
31
MSB
Input 5 Input 4
LSB MSB
t_PDDCDO
Input 2 Input 1
LSB MSB
Input 1
LSB
Input 32
MSB
Figure 17. Digital Interface Timing for Data Retrieval From a Single DDC232
Table 13. Timing for DDC232 Data Retrieval
SYMBOL
DESCRIPTION
MIN
TYP
t_PDCDV Propagation Delay from Falling Edge of CLK to DVALID Low
10
t_PDDCDV Propagation Delay from Falling Edge of DCLK to DVALID High
5
t_HDDODV Hold Time that DOUT is Valid Before the Falling Edge of DVALID
400
t_HDDODC Hold Time that DOUT is Valid After Falling Edge of DCLK
4
t_PDDCDO ⁽¹⁾ Propagation Delay from Falling Edge of DCLK to Valid DOUT
(1) With a maximum load of one DDC232 (4pF typical) with an additional load of 5pF.
MAX
25
UNITS
ns
ns
ns
ns
ns
20
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