DDC232_15 Datasheet, PDF (16/34 Pages) Texas Instruments – 32-Channel, Current-Input Analog-to-Digital Converter

DDC232
SBAS331D – AUGUST 2004 – REVISED APRIL 2010
TIMING EXAMPLES
Continuous Mode
A few timing diagrams help illustrate the operation of
the integrate/measure state machine. These
diagrams are shown in Figure 11 through Figure 16.
Table 9 gives generalized timing specifications in
units of CLK periods for Clk_4x = 0. If Clk_4x = 1,
these values increase by a factor of 4 because of the
internal clock divider. Values (in ms) for Table 9 can
be easily found for a given CLK.
Figure 11 shows a few integration cycles beginning
with initial power-up for a Cont mode example. The
www.ti.com
top signal is CONV and is supplied by the user. The
next line indicates the current state in the state
diagram. The following two traces show when
integrations and measurement cycles are underway.
The internal signal mbsy is shown next. Finally,
DVALID is given. As described in the data sheet,
DVALID goes active low when data are ready to be
retrieved from the DDC232. It stays low until DCLK is
taken high and then back low by the user. The text
below the DVALID pulse indicates the side of the
data available to be read and arrows help match the
data to the corresponding integration.
CONV
State 8
7
Integration
Status
m/r/az
Status
mbsy
6
Integrate B
5
Integrate A
m/r/az B
t_MRAZ
4
Integrate B
m/r/az A
5
Integrate A
m/r/az B
DVALID
t=0
Power−Up
SYMBOL
t_MRAZ
t_CMDR
t_CMDR
Side B
Data
Side A
Data
Figure 11. Continuous Mode Timing
Side B
Data
Table 9. Timing Specifications Generalized in CLK Periods
DESCRIPTION
Continuous mode, m/r/az cycle
Continuous mode, data ready
VALUE
(CLK Periods with Clk_4x = 0)
DDC232C
DDC232CK
1552 ± 2
1612 ± 2
1382 ± 2
1382 ± 2
16
Submit Documentation Feedback
Product Folder Link(s): DDC232
Copyright © 2004–2010, Texas Instruments Incorporated