DDC232_15 Datasheet, PDF (11/34 Pages) Texas Instruments – 32-Channel, Current-Input Analog-to-Digital Converter

DDC232
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Frequency Response
The frequency response of the DDC232 is set by the
front-end integrators and is that of a traditional
continuous time integrator, as shown in Figure 7. By
adjusting t_INT, the user can change the 3dB
bandwidth and the location of the notches in the
response. The frequency response of the ∆Σ
converter that follows the front-end integrator is of no
consequence because the converter samples a held
signal from the integrators. That is, the input to the
∆Σ converter is always a DC signal. Since the output
of the front-end integrators are sampled, aliasing can
occur. Whenever the frequency of the input signal
exceeds one-half of the sampling rate, the signal will
fold back down to lower frequencies.
0
−10
−20
−30
−40
−50
0.1
1
t_INT
t_INT
10
100
t_INT
t_INT
Frequency
Figure 7. Frequency Response
SBAS331D – AUGUST 2004 – REVISED APRIL 2010
CONFIGURATION REGISTER
Some aspects of device operation are controlled by
the onboard configuration register. The DIN_CFG,
CLK_CFG, and RESET pins are used to write to this
register. When beginning a write operation, hold
CONV low and strobe RESET; see Figure 8. Then
begin shifting in the configuration data on DIN_CFG.
Data are written to the configuration register most
significant bit first. The data are internally latched on
the falling edge of CLK_CFG. Partial writes to the
configuration register are not allowed—make sure to
send all 12 bits when updating the register.
Optional readback of the configuration register is
available immediately after the write sequence.
During readback, the 12-bit configuration data
followed by a 4-bit revision ID and the test pattern are
shifted out on the DOUT pin on the rising edge of
DCLK.
NOTE: Wth Format = 1, the test pattern is 304 bits,
with only the last 72 bits non-zero. This sequence of
outputs is repeated twice for each DDC232 and
daisy-chaining is supported in configuration readback.
Table 5 shows the test pattern configuration during
readback. Table 6 shows the timing for the
configuration register read and write operations.
Strobe CONV to begin normal operation.
Table 5. Test Pattern During Readback
Format BIT
0
1
TEST PATTERN
(Hex)
30F066012480F6h
30F066012480F69055h
TOTAL
READBACK BITS
512
640
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