DDC232_15 Datasheet, PDF (12/34 Pages) Texas Instruments – 32-Channel, Current-Input Analog-to-Digital Converter

DDC232
SBAS331D – AUGUST 2004 – REVISED APRIL 2010
t_RST
RESET
CLK_CFG
t_STCF
t_WTRST
DIN_CFG
MSB
Configuration Register Operations
t_WTWR
t_HDCF
LSB
Write Configuration Register Data
Read Configuration Register
and Test Pattern
DCLK
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Normal Operation
DOUT
CONV
MSB
LSB
Configuration
Register
Data
Test Pattern
NOTE: CLK must be running during Configuration Register write and read operations.
Figure 8. Configuration Register Write and Read Operations
SYMBOL
t_WTRST
t_WTWR
t_STCF
t_HDCF
t_RST
Table 6. Timing for the Configuration Register Read/Write
DESCRIPTION
Wait Required from Reset High to First Rising Edge of CLK_CFG
Wait Required from Last CLK-CFG of Write Operation to
First CLK_CFG of Read Operation
Set-Up Time from DIN_CFG to Falling Edge of CLK_CFG
Hold Time for DIN_CFG After Falling Edge of CLK_CFG
Pulse Width for RESET Active
MIN
TYP
2
2
10
10
1
MAX
UNITS
ms
ms
ns
ns
ms
12
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