DDC232_15 Datasheet, PDF (17/34 Pages) Texas Instruments – 32-Channel, Current-Input Analog-to-Digital Converter

DDC232
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In Figure 11, the first state is Ncont state 8. The
DDC232 always powers up in the Ncont mode. In this
case, the first state is 8 because CONV is initially
low. After the first two states, Cont mode operation is
reached and the states begin toggling between 4 and
5. From now on, the input is being continuously
integrated, either on side A or side B. The time
needed for the m/r/az cycle, t_MRAZ, is the same time
that determines the boundary between the Cont and
SBAS331D – AUGUST 2004 – REVISED APRIL 2010
Ncont modes described earlier in the Continuous and
Noncontinuous Operational Modes section. DVALID
goes low after CONV toggles in time t_CMDR, indicating
that data are ready to be retrieved.
See Figure 12 for the timing diagram of the internal
operations occurring during Continuous mode
operation. Table 10 gives the timing specifications of
the internal operations occurring during Continuous
mode operation.
End Integration Side A
Start Integration Side B
End Integration Side B
Start Integration Side A
End Integration Side A
Start Integration Side B
CONV
t_INT
t_INT
A/D Conversion
Odd Channels (Internal)
A/D Conversion
Even Channels (Internal)
DVALID
Side A
t_ADCONV
t_ADRST
Side A
t_ADCONV
Side B
t_ADRST
t_IRST
Side B
t_IRST
Side A
Data Ready
Side B
Data Ready
Figure 12. Internal Operation in Continuous Mode Timing
Side A
Table 10. Timing Characteristics for the Internal Operation in Continuous Mode
SYMBOL
DESCRIPTION
t_INT
t_ADCONV
t_ADRST
t_IRST
Integration Period (continuous mode)
A/D Conversion Time (internally controlled)
A/D Conversion Reset Time (internally controlled)
Integrator Reset Time (internally controlled)
DDC232C
(CLK = 5MHz, Clk_4x = 0)
MIN
TYP
MAX
320
1,000,000
135.6
3.2
36
DDC232CK
(CLK = 10MHz, Clk_4x = 0)
MIN
TYP
MAX
160
1,000,000
68
2.2
21.8
UNITS
ms
ms
ms
ms
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