AMC1204_15 Datasheet, PDF (20/37 Pages) Texas Instruments – AMC1204 20-MHz, Second-Order, Isolated Delta-Sigma Modulator

AMC1204, AMC1204B
SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
8 Application and Implementation
www.ti.com
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Digital Filter Usage
The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort
and hardware, is a sinc³-type filter, as shown in Equation 1:
3
H(z) =
1 - z^-OSR
1 - z^-1
(1)
This filter provides the best output performance at the lowest hardware size (count of digital gates). For an
oversampling rate (OSR) in the range of 16 to 256, this filter is a good choice. All the characterization in this
document is also done with a sinc³ filter with OSR = 256 and an output word width of 16 bits.
In a sinc³ filter response (shown in Figure 46 and Figure 47), the location of the first notch occurs at the
frequency of output data rate f_DATA = f_CLK/OSR. The –3-dB point is located at half the Nyquist frequency or
f_DATA/4. For some applications, it may be necessary to use another filter type with different frequency response.
Performance can be improved, for example, by using a cascaded filter structure. The first decimation stage could
be built of a sinc³ filter with a low OSR and the second stage using a high-order filter.
0
-10
-20
-30
-40
-50
-60
-70
-80
0
f_DATA = 20MHz/64 = 312.5kHz
-3dB: 81.9kHz
OSR = 64
200 400 600 800 1000 1200 1400 1600
Frequency (kHz)
30k
f_MOD = 20MHz
OSR = 64
25k _{FSR = 32768}
ENOB = 12 Bits
20k Settling Time =
3 ´ 1/f_DATA = 9.6ms
15k
10k
5k
0
0
5 10 15 20 25 30 35 40
Number of Output Clocks
Figure 46. Frequency Response Of The Sinc³ Filter
Figure 47. Pole Response Of The Sinc³ Filter
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
Figure 49 illustrates the ENOB of the AMC1204 and AMC1204B with different oversampling ratios. In this data
sheet, this number is calculated from SNR using Equation 2:
SNR = 1.76dB + 6.02dB ´ ENOB
(2)
An example code for an implementation of a sinc³ filter in an FPGA follows. For more information, see the
application note, Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control
Applications, (SBAA094), available for download at www.ti.com.
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