AMC1204_15 Datasheet, PDF (17/37 Pages) Texas Instruments – AMC1204 20-MHz, Second-Order, Isolated Delta-Sigma Modulator

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7 Detailed Description
AMC1204, AMC1204B
SBAS512E – APRIL 2011 – REVISED SEPTEMBER 2015
7.1 Overview
The AMC1204 and AMC1204B are single-channel, second-order, delta-sigma (ΔΣ) modulators designed for
medium- to high-resolution analog-to-digital conversions. The isolated output of the converter (DATA) provides a
stream of digital ones and zeros accurately representing the analog input voltage over time. The time average of
this serial output is proportional to the analog input voltage.
Functional Block Diagram shows a detailed block diagram of the AMC1204 and AMC1204B. The analog input
range is tailored to directly accommodate the voltage drop across a shunt resistor used for current sensing. The
SiO₂-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the
application report ISO72x Digital Isolator Magnetic-Field Immunity (SLLA181A). The external clock input
simplifies the synchronization of multiple current sense channels on system level. The extended frequency range
of up to 20 MHz supports higher performance levels compared to the other solutions available on the market.
7.2 Functional Block Diagram
Isolation Barrier
VINP
VINN
2nd-Order
DS Modulator
+
-
V_REF
+
-
3-State
Output
Buffer
DATA
POR
Buffer
2.5V
V_REF
V_REF
CLKIN
Figure 41. Detailed Block Diagram
7.3 Feature Description
7.3.1 Analog Input
The differential analog input of the AMC1204 and AMC1204B is implemented with a switched-capacitor circuit.
The AMC1204 and AMC1204B measure the differential input signal V_IN = (VINP – VINN) against the internal
reference of 2.5 V using internal capacitors that are continuously charged and discharged. Figure 42 shows the
simplified schematic of the AMC1204 and AMC1204B input circuitry; the right side of Figure 42 illustrates the
input circuitry with the capacitors and switches replaced by an equivalent circuit.
In Figure 42, the S₁ switches close during the input sampling phase. With the S₁ switches closed, C_DIFF charges
to the voltage difference across VINP and VINN. For the discharge phase, both S₁ switches open first and then
both S₂ switches close. C_DIFF discharges approximately to AGND + 0.8 V during this phase. This two-phase
sample/discharge cycle repeats with a period of t_CLKIN = 1/f_CLKIN. f_CLKIN is the operating frequency of the
modulator. The capacitors C_IP and C_IN are of parasitic nature and caused by bonding wires and the internal ESD
protection structure.
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