DS16EV5110A_15 Datasheet, PDF (2/25 Pages) Texas Instruments – Video Equalizer (3D+C) for DVI, HDMI Source/Repeater/Sink Applications

DS16EV5110A
SNLS301C – JULY 2008 – REVISED APRIL 2013
Typical Application
DVI/HDMI Source
SER A/V
Decoder
DS16EV5110A
5m 28 AWG DVI/HDMI Cable
DVI/HDMI Sink
DES/Display
Processor
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DVI/HDMI Source
SER/A/V
Decoder
25m 28 AWG DVI/HDMI Cable
DVI/HDMI Sink
DS16EV5110A
DES/Display
Processor
DVI/HDMI Source
SER/A/V
Decoder
25m 28 AWG DVI/HDMI Cable
1m 28 AWG DVI/HDMI Cable
DVI/HDMI Repeater
DS16EV5110A
DVI/HDMI Sink
DES/Display
Processor
PIN DESCRIPTIONS
Pin Name Pin Number I/O⁽¹⁾, Type
Description
HIGH SPEED DIFFERENTIAL I/O
C_IN−
C_IN+
1
I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50Ω terminating
2
resistor connects C_IN+ to VDD and C_IN- to VDD.
D_IN0−
D_IN0+
4
I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
5
resistor connects D_IN0+ to VDD and D_IN0- to VDD.
D_IN1−
D_IN1+
8
I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
9
resistor connects D_IN1+ to VDD and D_IN1- to VDD.
D_IN2−
D_IN2+
11
I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50Ω terminating
12
resistor connects D_IN2+ to VDD and D_IN2- to VDD.
C_OUT-
C_OUT+
36
O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
35
D_OUT0−
D_OUT0+
33
O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
32
D_OUT1–
D_OUT1+
29
O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
28
D_OUT2−
D_OUT2+
26
O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
25
Equalization Control
BST_0
BST_1
BST_2
23
I, LVCMOS BST_0, BST_1, and BST_2 select the equalizer boost level for EQ channels. BST_0, BST_1,
14
and BST_2 are internally pulled Low. See Table 2.
37
Device Control
EN
44
I, LVCMOS Enable Equalizer input. When held High, normal operation is selected. When held Low,
standby mode is selected. EN is internally pulled High. Signal is global to all Data and Clock
channels.
FEB
21
I, LVCMOS Force External Boost. When held High, the equalizer boost setting is controlled by the
BST_[0:2] pins. When held Low, the equalizer boost level is controlled through the SMBus
(see Table 1) control pins. FEB is internally pulled High.
SD
45
O, LVCMOS Equalizer Clock Channel Signal Detect Output. Produces a High when signal is detected.
POWER
V_DD
3, 6, 7,
Power V_DD pins should be tied to the V_DD plane through a low inductance path. A 0.1µF bypass
10, 13,
capacitor should be connected between each V_DD pin to the GND planes.
15, 46
GND
22, 24,
27, 30,
31, 34
GND
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Exposed Pad
DAP
GND
The exposed pad at the center of the package must be connected to the ground plane.
(1) Note: I = Input,O = Output, IO =Input/Output,
2
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