DS16EV5110A_15 Datasheet, PDF (16/25 Pages) Texas Instruments – Video Equalizer (3D+C) for DVI, HDMI Source/Repeater/Sink Applications

DS16EV5110A
SNLS301C – JULY 2008 – REVISED APRIL 2013
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Figure 10 shows the cable extension and jitter reduction obtained with the use of the equalizer. Table 7 lists the
various gain settings used versus cable length recommendations.
0.5
1.65 Gbps
0.4
1.30 Gbps
0.3
0.75 Gbps
Unequalized
0.2
0.1
00
Equalized
5 10 15 20 25 30 35 40
CAT 5 CABLE LENGTH (m)
Figure 10. Equalized vs. Unequalized Jitter Performance Over Cat5 Cable
General Recommendations
The DS16EV5110A is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner’s Manual for more detailed information on high-speed design tips as well as many other
available resources available addressing signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The TMDS differential inputs and outputs must have a controlled differential impedance of 100Ω. It is preferable
to route TMDS lines exclusively on one layer of the board, particularly for the input traces. The use of vias should
be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for
each side of a given differential pair. Route the TMDS signals away from other signals and noise sources on the
printed circuit board. All traces of TMDS differential inputs and outputs must be equal in length to minimize intra-
pair skew.
WQFN FOOTPRINT RECOMMENDATIONS
See application note AN-1187 (SNOA401) for additional information on WQFN packages footprint and soldering
information.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS16EV5110A is provided with an adequate power
supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent
layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and
GND planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.1µF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS16EV5110A. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2µF to 10µF should be incorporated in the power supply bypassing design as well.
These capacitors can be either tantalum or an ultra-low ESR ceramic and should be placed as close as possible
to the DS16EV5110A.
EQUIVALENT I/O STRUCTURES
Figure 11 shows the DS16EV5110A CML output structure and ESD protection circuitry.
Figure 12 shows the DS16EV5110A CML input structure and ESD protection circuitry.
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