DS16EV5110A_15 Datasheet, PDF (11/25 Pages) Texas Instruments – Video Equalizer (3D+C) for DVI, HDMI Source/Repeater/Sink Applications

DS16EV5110A
www.ti.com
SNLS301C – JULY 2008 – REVISED APRIL 2013
CLOCK CHANNEL
The clock channel incorporates a limiting amplifier, a DC offset correction, and a TMDS driver as shown in
Figure 4.
CLOCK CHANNEL SIGNAL DETECT
The DS16EV5110A features a signal detect circuit on the clock channel. The status of the clock signal can be
determined by either reading the Signal Detect bit (SD) in the SMBus registers (see Table 1) or by the state of
the SD pin. A logic High indicates the presence of a signal that has exceeded a specified threshold value (called
SD_ON). A logic Low means that the clock signal has fallen below a threshold value (called SD_OFF). These
values are programmed via the SMBus (Table 1). If not programmed via the SMBus, the thresholds take on the
default values for the SD_OFF and SD_ON values as indicated in Table 4. The Signal Detect threshold values
can be changed through the SMBus. All threshold values specified are DC peak-to-peak differential signals
(positive signal minus negative signal) at the input of the device.
Table 4. Clock Channel Signal Detect Threshold
Values
Bit 1
0
0
1
1
Bit 0
0
1
0
1
SD_OFF Threshold
Register 06 (mV)
40 (Default)
30
55
45
SD_ON Threshold
Register 05 (mV)
70 (Default)
55
90
75
D_IN+
D_IN-
BST_0 : BST_2
Data Channel
(0-2)
DC Offset Correction
Input
Equalizer
Limiting
Termination
BST
CNTL
Amplifier
EN
EN
EN
3
3
3
Boost Setting
SMBus Register
FEB
SMBus Reg.
REG7[0]
Figure 3. DS16EV5110A Data Channel
SMBus Reg.
REG3[7],
REG4[7],
REG4[3]
D_OUT+
D_OUT-
EN
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