BQ26100_15 Datasheet, PDF (19/29 Pages) Texas Instruments – Based Security and Authentication IC

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bq26100
SLUS696B – JUNE 2006 – REVISED AUGUST 2015
7.6.1.2 Control and Version Registers – Memory Function Command 0x88 (Read) and 0x77 (Write)
The control register starts authentication, clears the message/digest values, and flags when the authentication
process has completed. The version register is used to determine the silicon revision.
Table 7. General Memory Space Addressing
ADDRESSES
0x0001
0x0000
FUNCTION
Silicon Revision Number
Control Register
The bits of the Control register are as follows:
Figure 22. Control Register
NAME
POR STATUS
BIT 7
PROGK1
0
BIT 6
PROGK0
0
BIT 5
RSVD
0
BIT 4
CLEAR
0
BIT 3
RSVD
0
BIT 2
POR
1
BIT 1
DONE
0
BIT 0
AUTH
0
PROGK1 If LOCKK1 is 1 (see Status Register), writing this bit to 1 enables the programming of Device Key 1.
Further information about the programming of the keys is found in the SHA-1 section.
PROGK0 If the LOCKK0 bit is 1 (see Status Register), writing this bit to 1 enables the programming of Device
Key 0. Further information about the programming of the keys is found in the SHA-1 section.
RSVD These bits are reserved for future use. They should always be written to 0.
CLEAR
Writing this bit to 1 clears the message/digest registers. This can be done before the message is
written to ensure that all data values are known or after the digest is read to clear the HMAC
calculation output. The bq26100 device resets the bit back to 0.
POR
This bit is set when the device comes out of a POR condition. The bit can be written to 0 to clear the
flag. Writing the bit to 1 has no effect on device operation.
DONE
This bit is set when the device completes the HMAC calculation. The host should poll for this bit to
determine when the digest is available for reading. This bit is automatically cleared when the AUTH
bit is written to 1. This bit is also cleared at POR.
AUTH
This bit is set to initiate the HMAC calculation. This bit is automatically cleared when the DONE bit is
written to 1.
Read
Control
Flow
M/F = 0x88
Write
Control
Flow
M/F = 0x77
(1) _{Master TX:}
16-bit address, A
(1) _{Master TX:}
16-bit address, A
Master RX:
CRC of M/F cmd & A
Master TX:
8-bit data, D
Master RX:
8-bit data @ A
A=A+1
A = 0x0001?
NO
YES
Master RX:
CRC of all data transmitted
ROM
Function
Flow
Master RX:
CRC of M/F cmd, A & D
Master RX:
D
A = 0x0001?
YES
ROM
Function
Flow
Master RX:
CRC of preloaded
A[7:0] & shifted D
NO
Master TX:
8-bit data, D
CRC = 0x01
A = A +1
(1) 16-Bit address is sent with lower 8-bit address followed by higher 8-bit address with least significant bit first.
Figure 23. Control Register Write/Read Flows
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