DS92LV8028_13 Datasheet, PDF (18/22 Pages) Texas Instruments – 8 Channel 10:1 Serializer

DS92LV8028
SNLS152I – NOVEMBER 2001 – REVISED APRIL 2013
Pin Number
C7, C9, C10, D6, D7, D9, E5, E7,
G7
C6, C8, C11, D5, D8, D10, E6,
E8, F7
Name
AGND
AVDD
B12 BIST_ACT
A13, B13, D11, E11
BIST_SEL
(0:3)
M14
DEN
A2, A3, A12, B2, B3, C2, C4,
D12, E1, E2, E9, E10, E12, E13,
E14, F6, F10, H10, K6, K10,
M13, P1
E3, E4, F1, F2, F3, F4, F11, F12,
G1, G2, G3, G4, G11, G12, G14,
H1, H2, H3, H4, H11, H12, H13,
H14, J1, J2, J3, J4, J11, J12,
J13, J14, K1, K2, K3, K4, K11,
K12, K13, K14, L3, L4, L5, L6,
L7, L8, L9, L10, L11, L12, L13,
L14, M3, M4, M5, M6, M7, M8,
M9, M10, M11, N3, N4, N5, N6,
N7, N8, N9, N10, N11, P2, P3,
P4, P5, P6, P7, P8, P9, P10 P11,
P12
B11-A11, B10-A10, B9-A9, B8-
A8, B7-A7, A6-B6, A5-B5, A4-B4
A1, B1, C3, C5, D4, D13, D14,
F5, F8, F9, F13, G6, G10, G13,
H7,
DGND
DINnx
Doutn±
DVDD
N14 MS_PWDN
G5, G8, G9, H5, H6, H8, H9, J5,
J6, J7, J9, J10
C1, D1
D2, D3
NC (1:12)
PGND
PVDD
N1, N2, N13, M1, M2, M12, P13,
P14
PWDN (0:7)
J8, K5, K7, K8, K9, L1, L2, N12 SYNC (0:7)
C13
TCK
B14
TDI
C14
TDO
A14
TMS
C12 TRSTN
F14
TCLK
(1) BIST_SEL pins are pull-up internally.
Table 1. Pin Descriptions
Type
Analog ground.
Description
www.ti.com
3.3 V
CMOS
I
3.3 V
CMOS
I
3.3 V
CMOS
I
Analog power supply.
BIST Active. Control pin for BIST mode enable.When BIST_ACT = H
and BIST_SEL (0:3) = 0H to 8H, device will go to BIST mode
accordingly. See Truth Table (BIST mode) Default at Low
BIST select. Control pins for which serializer is set for BIST mode.
See Truth Table (BIST mode) ⁽¹⁾ Default at V_DD
Serializer output data enable. Enable data output DOUTn (0:9). n =
serializer number. When driven low, puts the Bus LVDS outputs in
TRI-STATE. Default at Low.
Digital Ground.
3.3 V
CMOS
I
Data input. Inputs for the ten bit serializers. n = serializer number, x =
bit number. Default at Low.
Bus LVDS
O
Bus LVDS differential outputs. n = serializer number.
Digital power supply.
3.3 V
CMOS
I
3.3 V
CMOS
I
3.3 V
CMOS
I
3.3 V
CMOS
I
Master Powerdown. MS_PWDN driven low shuts down the PLL and
TRI-STATE all outputs, putting the device into a low power ’sleep’
mode. Default at Low.
No connect.
PLL ground.
PLL power supply.
Individual Powerdown. PWDN (0:7) driven low puts individual
serializer into TRI-STATE, low power ’sleep’ mode. Default at Low.
SYNC pattern enable. When driven high for a mininum of 4 cycles,
SYNC patterns will be transmitted on the Bus LVDS serial output. The
SYNC pattern sent by the serializer consists of six ones and six zeros
switching at the input clock rate. SYNC pattern continues to be sent if
SYNC continues at high. Default at Low. See Functional Description.
JTAG pin. Reserved for future use. Leave this pin floating.
JTAG pin. Reserved for future use. Leave this pin floating.
JTAG pin. Reserved for future use. Leave this pin floating.
JTAG pin. Reserved for future use. Leave this pin floating.
JTAG pin. Reserved for future use. Leave this pin floating.
Transmit Clock. Input for 25MHz - 66 MHz (nominal) system clock.
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