DS92LV8028_13 Datasheet, PDF (14/22 Pages) Texas Instruments – 8 Channel 10:1 Serializer

DS92LV8028
SNLS152I – NOVEMBER 2001 – REVISED APRIL 2013
APPLICATION INFORMATION
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USING THE DS92LV8028
The DS92LV8028 is an easy to use serializer that combines eight 10:1 serializers into a single chip with a
maximum payload of 5.28Gbps. Each of the eight serializers accepts 10 or less data bits. The serializers then
multiplex the data into a serial data stream with embedded clock bits and route to the LVDS output at up to
660Mbps per channels. The LVDS output is a 5 ma current loop driver that can be used for point-to-point and
lightly loaded multidrop applications. Each of the eight channels has their own serializer function but share a
single Transmit Clock (TCLK) with a single PLL for the entire chip. The data on all eight channels is latched into
the device with the rising edge of TCLK and the data stream is compatible with the DS92LV1210,
DS92LV1212A, DS92LV1224, DS92LV1260 deserializers from TI.
If using less than 10 bits of data, it is recommended to tie off adjacent bits to the embedded clock bits to prevent
causing a RMT in the data payload. For example, if only using 8 bits, tie D0 High and D9 Low.
Power Considerations
All CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the
constant current source nature of the LVDS outputs minimize the slope of the speed vs. I_CC curve of CMOS
designs.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the BLVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high-frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitic, especially proven effective at high frequencies above
approximately 50MHz, and makes the value and placement of external bypass capacitors less critical. External
bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values
in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals.
Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and
extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to
the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are
recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller
value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the
50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and
ground pins straight to the power and ground plane, with the bypass capacitors connected to the plane with via
on both ends of the capacitor. Connecting a power or ground pin to an external bypass capacitor will increase
the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. User must pay attention to the resonance frequency of these
external bypass capacitors, usually in the range of 20-30MHz range. To provide effective bypassing, very often,
multiple capacitors are used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two via from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate CMOS (TTL) swings away from the LVDS
lines to prevent coupling from the CMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms
are typically recommended for LVDS interconnect. The closely-coupled lines help to ensure that coupled noise
will appear as common-mode and thus is rejected by the receivers. Also the tight coupled lines will radiate less.
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