DS92LV8028_13 Datasheet, PDF (10/22 Pages) Texas Instruments – 8 Channel 10:1 Serializer

DS92LV8028
SNLS152I – NOVEMBER 2001 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
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The DS92LV8028 combines eight 10:1 serializers into a single chip. Each of the eight serializers accepts 10 or
less data bits. The serializers then multiplex the data into a serial stream with embedded clock bits and route to
the LVDS output. The LVDS output is a 5 mA current loop driver. It provides enough drive for point-to-point and
lightly loaded multidrop applications. The serialized data stream is compatible with the DS92LV1210,
DS92LV1212A, DS92LV1224, DS92LV1260 10-bit deserializers from TI.
Each of the eight channels on the DS92LV8028 has their own serializer function but share a single PLL. There is
a single Transmit Clock (TCLK) for all eight channels. The data on all eight 10-bit interfaces is latched into the
device with the rising edge of TCLK. Each of the serialized data streams is independent of the others and
includes the embedded clock information. The skew between the serializer outputs is minimal.
There is a master power-down signal (MS_PWDN) to put the entire device into a low power consumption state.
In addition, there is a power-down control signal for each of the eight channels. This allows the device to
efficiently operate as one to eight 10-bit serializers.
The @SPEED TEST signal initiates the sending of a random data pattern over the LVDS links. This allows for
testing the links for bit error rates at the frequency they will be carrying data. In addition, the JTAG boundary
scan circuits will be added to the device at a later date. The JTAG signal pins are reserved on this version. See
package connection diagram.
The DS92LV8028 has four operating modes. They are the Initialization, Data Transfer, Resynchronization,
@SPEED TEST states. In addition, there are two passive states: Power-down and TRI-STATE.
The following sections describe each operating mode and passive state.
Initialization
Before the '8028 serializes and transmits data, it and the receiving deserializer device(s) must initialize the link.
Initialization refers to synchronizing the Serializer's and the Deserializer's PLLs to local clocks. The local clocks
should be the same frequency, or within the specified range if from different sources. After all devices
synchronize to local clocks, the Deserializers synchronize to the Serializers as the second and final initialization
step.
Step 1: After applying power to the serializer, the outputs are held in TRI-STATE and the on-chip power-
sequencing circuitry disables the internal circuits. When Vcc reaches VccOK (2.1V), the PLL in the serializer
begins locking to the local clock (TCLK). A local on-board data source or other source provides the specified
clock input to the TCLK pin.
After locking to TCLK, the serializer is now ready to send data or SYNC patterns, depending on the level of the
SYNC input or a data stream at the data inputs. The SYNC pattern sent by the serializer consists of six ones and
six zeros switching at the input clock rate.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. (Refer to the
deserializer data sheet for operation details during this step of the Initialization State.) The Deserializer identifies
the rising clock edge in a synchronization pattern or non-repetitive data pattern. Depending on the data pattern
that it is being transmitted, the Deserializer will synchronize to the data stream from the Serializer after some
delay. At the point where the Deserializer's PLL locks to the embedded clock, the LOCK pin goes low and valid
data appears on the output.
The user's application determines control of the SYNC signal input. One recommendation is a direct feedback
loop from the LOCK pin on the deserializer. The serializer stops sending SYNC patterns when the SYNC input
returns to a low state.
Data Transfer
After initialization, the serializer accepts data from the inputs DINn0 to DINn9. The serializer uses the rising edge
of the TCLK input to latch incoming data. If the SYNCn input is high for 4 TCLK cycles, the data on DINn0-DINn9
is ignored and SYNC pulses are transferred.
The serial data stream includes a start bit and stop bit appended by the serializer, which frame the ten data bits.
The start bit is always high and the stop bit is always low. The start and stop bits also function as clock bits
embedded in the serial stream.
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