DS92LV8028_13 Datasheet, PDF (11/22 Pages) Texas Instruments – 8 Channel 10:1 Serializer

DS92LV8028
www.ti.com
SNLS152I – NOVEMBER 2001 – REVISED APRIL 2013
The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if
TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial
'payload' rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data rate is 40 X 10
= 400 Mbps. TCLK is provided by the data source and must be in the range 25 MHz to 66 MHz nominal.
The serializer outputs (DO0± – DO7±) can drive a point-to-point connection or lightly loaded multidrop
connections. The outputs transmit data when the driver enable pin (DEN) is high, MS_PWDN and PWDNn are
high, and SYNCn is low. When DEN is driven low, all the serializer output pins will enter TRI-STATE.
When any one of eight attached Deserializer channels synchronizes to the input from the Serializer, it drives its
LOCK pin low and synchronously delivers valid data on the output. The Deserializer locks to the embedded
clock, uses it to generate multiple internal data strobes, and drives the embedded clock on the RCLK pin. The
RCLK is synchronous to the data on the ROUT pins. While LOCK is low, data on ROUT is valid. Otherwise,
ROUT is invalid.
Resynchronization
Whenever one of the connected DS92LV1212, '1212A, '1224, or '1260 deserializers loses lock, it will
automatically try to resynchronize to the data stream from the serializer. If the data stream is not a repetitive
pattern, then the deserializer will automatically lock.
For example, if the deserializer's received embedded clock edge is not detected two times in succession, the
PLL loses lock and the LOCK pin is driven high. The '1212, '1212A, '1224, or '1260 deserializers will
automatically begin searching for the embedded clock edge. If it is a random data pattern, the deserializer will
lock to that stream. If the data pattern is repetitive, the deserializer’s PLL will not lock in order to prevent the
deserializer to lock to the data pattern rather than the clock. We refer to such patterns as repetitive-multiple-
transition, RMT.
Therefore, if the data stream is not random data or the deserializer is the DS92LV1210, there needs to be a
feedback path from the deserializer to the serializer. This feedback path can be as simple as connecting the
deserializer's LOCK pin to the serializer's SYNC pin. This will automatically signal the serializers to send SYNC
patterns whenever the deserializer loses lock.
The user has the choice of allowing the deserializer to resynchronize to the data stream, or to force
synchronization by pulsing the Serializer SYNC pin. This scheme is left up to the user discretion.
Power-down
The Power-down state is a low power sleep mode that the Serializer and Deserializer typically occupy while
waiting for initialization, or to reduce power when there are no pending data transfers. The DS92LV8028
serializers enter Power-down when MS_PWDN is driven low. In Power-down, the PLL stops and the outputs go
into TRI-STATE. To exit Power-down, the system drives MS_PWDN high.
Each of the serializers in the '8028 also has an individual power down, PWDNn control pin. This control enables
the deactivation of individual serializers while allowing others to operate normally. The benefit is that spare
serializers can be allocated for backup operation, but not consuming power until employed for data transfers.
Upon exiting Power-down, the Serializer enters the Initialization state. The system must then allow time to
initialize before data transfer can begin.
TRI-STATE
When the system drives DEN pin low, the serializer outputs enter TRI-STATE. This will TRI-STATE the output
pins (DO0± to DO7±). When the system drives DEN high, the serializers will return to the previous state as long
as all other control pins remain static (PWDNn, TCLK, SYNCn, and DINn[0:9]).
@SPEED Test Feature
Since the high-speed LVDS serial data transmission line quality is essential to the chipset operation, a means of
checking this signal integrity is built into the DS92LV8028 serializer. Each Serializer channel has the ability to
transfer an internally generated PRBS data pattern. This pattern traverses the transmission line to the
deserializer. Specific deserializers (SCAN921224 for example) have the complement PRBS pattern verification
circuit. The deserializer checks the data pattern for bit errors and reports any errors on the test verification pins
on the deserializer.
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