DS92LV8028_13 Datasheet, PDF (15/22 Pages) Texas Instruments – 8 Channel 10:1 Serializer

DS92LV8028
www.ti.com
SNLS152I – NOVEMBER 2001 – REVISED APRIL 2013
TRANSMISSION MEDIA
The DS92LV8028 Serializers can be used in point-to-point configuration of a backplane across PCB traces or
through cable interconnect. In point-to-point configurations the transmission media needs only to be terminated at
the receiver end. The DS92LV8028 may also be used with double terminations for a total load or 50 Ohms for
use in certain limited multidrop applications. Termination impedances lower than 50 Ohms is not recommended.
TERMINATION
Termination of the LVDS interconnect is required. For point-to-point applications termination should be located at
the load end. Nominal value is 100 Ohms to match the line's differential impedance. Place the resistor as close
to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver.
Additional general guidance can be found in the LVDS Owner's Manual - available in PDF format from the TI
web site at SNLA187
DS92LV8028 BLVDS SERIALIZER BYPASS RECOMMENDATIONS
General device specific guidance is given below. Exact guidance can not be given as it is dictated by other board
level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated
circuit power supply needs.
For a typical application circuit, please see Figure 12.
DVDD = DIGITAL SECTION POWER SUPPLY
These pins supply the digital portion of the device. A 0.1uF capacitor is sufficient for these pins.
PVDD = PLL SECTION POWER SUPPLY
The PVDD pin supplies the PLL circuit. The PLL(s) require clean power for the minimization of Jitter. A supply
noise frequency in the 300kHZ to 1MHz range can cause increased output jitter. Certain power supplies may
have switching frequencies or high harmonic content in this range. If this is the case, filtering of this noise
spectrum may be required. A notch filter response is best to provide a stable VDD, suppression of the noise
band, and good high-frequency response (clock fundamental). This may be accomplished with a pie filter (CRC
or CLC). The pie filter should be located close to the PVDD power pin. Separate power planes for the PVDD pins
is typically not required.
AVDD = LVDS SECTION POWER SUPPLY
The AVDD pin supplies the LVDS portion of the circuit. The DS92LV8028 has nine AVDD pins. Due to the nature
of the design, current draw is not excessive on these pins. A 0.1uF capacitor is sufficient for these pins. If space
is available, a 0.01uF may be used in parallel with the 0.1uF capacitor for additional high frequency filtering.
GROUNDs
The AGND pin should be connected to the signal common in the cable for the return path of any common-mode
current. Most of the LVDS current will be odd-mode and return within the interconnect pair. A small amount of
current may be even-mode due to coupled noise, and driver imbalances. This current should return via a low
impedance known path.
A solid ground plane is recommended for DVDD, PVDD and AVDD. Using a split plane may have a potential
problem of ground loops, or difference in ground potential at various ground pins of the device.
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