TMS320C6671_16 Datasheet, PDF (163/238 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

Figure 7-31 shows the C6671 interrupt topology.
Figure 7-31 TMS320C6671 Interrupt Topology
TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756E—March 2014
15 Reserved Secondary Events
89 Core-only Secondary Events
56 Common Events
CIC0
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
8 Broadcast Events from CIC0
Core0
56 Common Events
44 Reserved Secondary Events
60 EDMA3CC-only
Secondary Events
CIC2
31 Primary Events
26 Secondary Events
7 Reserved Primary Events
33 Primary Events
24 Secondary Events
7 Reserved Primary Events
EDMA3
CC1
EDMA3
CC2
45 Reserved Secondary Events
35 Events
CIC3
32 Primary Events
32 Secondary Events
8 Primary Events
8 Secondary Events
HyperLink
EDMA3
CC0
Figure 7-32 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x
DSP CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 72.
Figure 7-32 TMS320C6671 System Event Inputs — C66x CorePac Primary Interrupts (Part 1 of 4)
Input Event Number Interrupt Event
Description
0
EVT0
Event combiner 0 output
1
EVT1
Event combiner 1 output
2
EVT2
Event combiner 2 output
3
EVT3
4
TETBHFULLINTn ⁽¹⁾
5
TETBFULLINTn ⁽¹⁾
6
TETBACQINTn ⁽¹⁾
7
TETBOVFLINTn ⁽¹⁾
8
TETBUNFLINTn ⁽¹⁾
Event combiner 3 output
TETB is half full
TETB is full
Acquisition has been completed
Overflow condition interrupt
Underflow condition interrupt
9
EMU_DTDMA
10
MSMC_mpf_errorn ⁽²⁾
ECM interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
Memory protection fault indicators for local core
11
EMU_RTDXRX
RTDX receive complete
12
EMU_RTDXTX
RTDX transmit complete
13
IDMA0
IDMA channel 0 interrupt
14
IDMA1
15
SEMERRn ⁽³⁾
IDMA channel 1 interrupt
Semaphore error interrupt
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Peripheral Information and Electrical Specifications 163