TMS320C6671_16 Datasheet, PDF (125/238 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756E—March 2014
7.3.4 SmartReflex
Increasing the device complexity increases its power consumption and with the smaller transistor structures
responsible for higher achievable clock rates and increased performance, comes an inevitable penalty: increasing the
leakage currents. Leakage currents are present in any active circuit, independent of clock rates and usage scenarios.
This static power consumption is mainly determined by the transistor type and process technology used in the
manufacture of the device. Higher clock rates also increase dynamic power — the power used when transistors
switch. The dynamic power depends mostly on a specific usage scenario, clock rates, and I/O activity.
Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while
maintaining device performance.
SmartReflex in the TMS320C6671 is a feature that allows the core supply voltage to be optimized based on the
process corner of the device. Voltage selection is done using four VCNTL pins that control the output voltage of the
core voltage regulator supplying the device. Each TMS320C6671 device in an application requires a separate core
voltage regulator. For information on the implementation of SmartReflex, see the Power Consumption Summary for
KeyStone C66x Devices application report and the Hardware Design Guide for KeyStone I Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 72.
Table 7-5
SmartReflex 4-Pin VID Interface Switching Characteristics
(see Figure 7-5)
No.
Parameter
1 td(VCNTL[2:0]-VCNTL[3]) Delay Time - VCNTL[2:0] valid after VCNTL[3] low
2 toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low
3 td(VCNTL[2:0]-VCNTL[3]) Delay Time - VCNTL[2:0] valid after VCNTL[3] high
4 toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high
5 VCNTL being valid to CVDD being switched to SmartReflex Voltage ⁽²⁾
End of Table 7-5
1 C = 1/SYSCLK1 frequency in ms
2 SmartReflex voltage must be set before execution of application code
Figure 7-5 SmartReflex 4-Pin VID Interface Timing
Min
Max
Unit
300.00 ns
0.07 172020C ⁽¹⁾ ms
300.00 ns
0.07 172020C ms
10 ms
CVDD
VCNTL[3]
VCNTL[2:0]
IV*
* IV = Initial Voltage
† _{SRV = Smart Reflex Voltage}
SRV^†
4
5
1
3
LSB VID[2:0]
2
MSB VID[5:3]
Note—The initial CVDD voltage (IV) at power on will be 1.1 V nominal and it must transition to the VID
set value immediately after being presented on the VCNTL pins. This is required to maintain full power
functionality and reliability targets specified by TI.
Copyright 2014 Texas Instruments Incorporated
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