TMS320C6671_16 Datasheet, PDF (122/238 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756E—March 2014
7.3.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 7-4 and defined in Table 7-3.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level
within 20 ms.
Figure 7-4 IO Before Core Power Sequencing
Power Stabilization Phase Device Initialization Phase
POR
RESETFULL
GPIO Config
Bits
2a
RESET
2b
CVDD
CVDD1
3c
3a
5
7
8
9
10
6
1
DVDD18
DVDD15
REFCLKP&N
4
3b
DDRCLKP&N
RESETSTAT
122 Peripheral Information and Electrical Specifications
Copyright 2014 Texas Instruments Incorporated
Submit Documentation Feedback