TMS320C6671_16 Datasheet, PDF (120/238 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756E—March 2014
REFCLK must always be active before POR can be removed. Core-before-IO power sequencing is defined in
Table 7-2.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level
within 20ms.
Figure 7-3 Core Before IO Power Sequencing
Power Stabilization Phase Device Initialization Phase
POR
RESETFULL
7
8
GPIO Config
Bits
RESET
1
CVDD
4b
2c
2a
CVDD1
3
DVDD18
9
10
6
4a
DVDD15
5
REFCLKP&N
2b
DDRCLKP&N
RESETSTAT
120 Peripheral Information and Electrical Specifications
Copyright 2014 Texas Instruments Incorporated
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