LMH6881 Datasheet, PDF(16/35 Page) Texas Instruments – Small Signal Bandwidth: 2400 MHz

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LMH6881 Datasheet, PDF (16/35 Pages) Texas Instruments – Small Signal Bandwidth: 2400 MHz

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LMH6881

SNOSC72F â JUNE 2012 â REVISED FEBRUARY 2015

www.ti.com

A shutdown pin (SD == 0, amplifier on, SD == 1, amplifier off) is provided to reduce power consumption by

disabling the highest power portions of the amplifier. The digital control circuit is not shut down and will preserve

the last active gain setting during the disabled state. See the Typical Characteristics section for disable and

enable timing information. The SD pin is functional in parallel mode only and disabled in serial mode.

CONTROL LOGIC

LMH6881

Shutdown

2 dB Step

4 dB Step

8 dB Step

16 dB Step

Figure 39. Parallel Mode Connection

7.5.1.2 SPI-Compatible Serial Interface

The serial interface allows a great deal of flexibility in gain programming and reduced board complexity. The

LMH6881 serial interface is a generic 4-wire synchronous interface that is compatible with SPI-type interfaces

that are used on many microcontrollers and DSP controllers. Using only four wires, the SPI mode offers access

to the 0.25-dB gain steps of the amplifier.

For systems where gain is changed only infrequently, or where only slower gain changes are required, serial

mode is the best choice. To place the LMH6881 into serial mode the SPI pin (Pin 5) should be put into the logic

high state. Alternatively the SPI pin can be connected directly to the 5-V supply bus. In this configuration the pins

function as shown in Table 1. The SPI interface uses the following signals: clock input (CLK), serial data in (SDI),

serial data out (SDO), and serial chip select (CS). The chip-select pin is active low meaning the device is

selected when the pin is low.

The SD pin is inactive in the serial mode. This pin can be left disconnected for serial mode. The SPI interface

has the ability to shut down the amplifier without using the SD pin.

The CLK pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the

rising edge and to source the output data on the SDO pin on the falling edge. The user may disable clock and

hold it in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is

enabled or disabled. The clock pulse-width minimum is equal to one setup plus one hold time, or 6 ns.

The CS pin is the chip-select pin. This pin is active low; the chip is selected in the logic low state. Each assertion

starts a new register access - that is, the SDATA field protocol is required. The user is required to deassert this

signal after the 16th clock. If the CS pin is deasserted before the 16th clock, no address or data write will occur.

The rising edge captures the address just shifted in and, in the case of a write operation, writes the addressed

Specifications section.

The SDI pin is the input pin for the serial data. Each write cycle is 16-bits long.

The SDO pin is the data output pin. This output is normally at a high impedance state, and is driven only when

CS is asserted. Upon CS assertion, contents of the register addressed during the first byte are shifted out with

the second 8 SCLK falling edges. The SDO pin is a current output and requires external bias resistor to develop

the logic 1 voltage would be 2.5 V. In the logic 0 state, the SDO output is off and no current flows, so the bias

resistor will pull the voltage to 0 V.

Each serial interface write access cycle is exactly 16 bits long as shown in Figure 40.

The external bias resistor means that in the high-impedance state the SDO pin impedance is equal to the

external bias resistor value. If busing multiple SPI devices make sure that the SDO pins of the other devices can

drive the bias resistor.

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