LMH6881 Datasheet, PDF (15/35 Pages) Texas Instruments – Small Signal Bandwidth: 2400 MHz

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LMH6881
SNOSC72F – JUNE 2012 – REVISED FEBRUARY 2015
7.5 Programming
7.5.1 Digital Control of the Gain and Power-Down Pins
The LMH6881 was designed to interface with 2.5-V to 5-V CMOS logic circuits. If operation with 5-V logic is
required, care should be taken to avoid signal transients exceeding the supply voltage of the amplifier. Long,
unterminated digital signal traces should be avoided. Signal voltages on the logic pins that exceed the device
power supply voltage may trigger ESD protection circuits and cause unreliable operation. Some digital input-
output pins have different functions depending on the digital control mode. Table 1 shows the mapping of the
digital pins. These functions for each pin will be described in the sections Parallel Interface and SPI-Compatible
Serial Interface.
Table 1. Pins With Dual Functions
Pin
SPI = 0
SPI = 1
3
D1
SDI
4
D0
SDO ⁽¹⁾
15
D2
CLK
16
D3
CS (active low)
(1) Pin 4 requires external bias. See SPI-Compatible Serial Interface section for Details.
7.5.1.1 Parallel Interface
Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space
dedicated to control lines. To place the LMH6881 into parallel mode the SPI pin (pin 5) is set to the logical zero
state. Alternately the SPI pin can be connected directly to ground. The SPI pin has a weak internal resistor to
ground. If left unconnected, the amplifier will operate in parallel mode.
In parallel mode the gain can be changed in 2-dB steps with a 4-bit gain control bus. The attenuator control pins
are internally biased to logic high state with weak pull-up resistors, with the exception of D0 which is biased low
due to the shared SDO function. If the control bus is left unconnected, the amplifier gain will be set to 6 dB.
Table 2 shows the gain of the amplifier when controlled in parallel mode.
Table 2. Amplifier Gain for All Control Pin Combinations
CONTROL PINS LOGICAL LEVEL IN PARALLEL MODE
D3
D2
D1
D0
1
X
1
X
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
DECIMAL VALUE
10 - 15
9
8
7
6
5
4
3
2
1
0
AMPLIFIER
VOLTAGE GAIN
[dB]
6
8
10
12
14
16
18
20
22
24
26
For fixed-gain applications the attenuator-control pins should be connected to the desired logic state instead of
relying on the weak internal bias. Data from the gain-control pins directly drive the amplifier gain circuits. To
minimize gain change glitches all gain pins should be driven with minimal skew. If gain-pin timing is uncertain,
undesirable transients can be avoided by using the shutdown pin to disable the amplifier while the gain is
changed. Gain glitches are most likely to occur when multiple bits change value for a small gain change, such as
the gain change from 10 dB to 12 dB which requires changing all 4 gain-control pins.
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