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CC2650MODA Datasheet, PDF (16/40 Pages) Texas Instruments – Low energy Wireless MCU Module
CC2650MODA
SWRS187A – AUGUST 2016 – REVISED AUGUST 2016
www.ti.com
5.22 Thermal Resistance Characteristics for MOH Package
NAME
DESCRIPTION
°C/W (1) (2)
AIR FLOW (m/s)(3)
RΘJC
RΘJB
RΘJA
RΘJMA
PsiJT
PsiJB
Junction-to-case
Junction-to-board
Junction-to-free air
Junction-to-moving air
Junction-to-package top
Junction-to-board
20.0
15.3
29.6
0
25.0
1
8.8
0
14.8
0
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
(3) m/s = meters per second.
5.23 Timing Requirements
MIN NOM MAX UNIT
Rising supply-voltage slew rate
0
100 mV/µs
Falling supply-voltage slew rate
Falling supply-voltage slew rate, with low-power flash settings(1)
0
20 mV/µs
3 mV/µs
Positive temperature gradient in standby(2)
CONTROL INPUT AC CHARACTERISTICS(3)
No limitation for negative
temperature gradient, or
outside standby mode
5 °C/s
RESET_N low duration
SYNCHRONOUS SERIAL INTERFACE (SSI)(4)
1
µs
S1 (SLAVE)(5)
S2 (5)
S3 (5)
tclk_per
tclk_high
tclk_low
SSIClk period
SSIClk high time
SSIClk low time
12
65024
System
clocks
0.5
tclk_per
0.5
tclk_per
(1) For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDD input capacitor (see
Section 7.1.1) must be used to ensure compliance with this slew rate.
(2) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see
Section 5.14).
(3) TA = –40°C to +85°C, VDD = 1.7 V to 3.8 V, unless otherwise noted.
(4) Tc = 25°C, VDD = 3.0 V, unless otherwise noted. Device operating as slave. For SSI master operation, see Section 5.24.
(5) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
5.24 Switching Characteristics
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
WAKEUP AND TIMING
Idle → Active
14
Standby → Active
151
Shutdown → Active
1015
UNIT
µs
µs
µs
16
Specifications
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