CC2650MODA Datasheet, PDF (13/40 Pages) Texas Instruments – Low energy Wireless MCU Module

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CC2650MODA
SWRS187A – AUGUST 2016 – REVISED AUGUST 2016
5.15 ADC Characteristics
T_c = 25°C, V_DD = 3.0 V and voltage scaling enabled, unless otherwise noted ⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN
TYP
Input voltage range
0
Resolution
12
Sample rate
Offset
Internal 4.3-V equivalent reference⁽²⁾
2
Gain error
Internal 4.3-V equivalent reference⁽²⁾
2.4
DNL ⁽³⁾
Differential nonlinearity
>–1
INL ⁽⁴⁾
Integral nonlinearity
±3
Internal 4.3-V equivalent reference⁽²⁾, 200 ksps,
9.6-kHz input tone
9.8
ENOB
Effective number of bits VDD as reference, 200 ksps, 9.6-kHz input tone
10
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
11.1
Internal 4.3-V equivalent reference⁽²⁾, 200 ksps,
9.6-kHz input tone
–65
THD
Total harmonic
distortion
VDD as reference, 200 ksps, 9.6-kHz input tone
–69
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
–71
Internal 4.3-V equivalent reference⁽²⁾, 200 ksps,
9.6-kHz input tone
60
SINAD
Signal-to-noise and
and SNDR distortion ratio
VDD as reference, 200 ksps, 9.6-kHz input tone
63
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
69
Internal 4.3-V equivalent reference⁽²⁾, 200 ksps,
9.6-kHz input tone
67
SFDR
Spurious-free dynamic
range
VDD as reference, 200 ksps, 9.6-kHz input tone
72
Internal 1.44-V reference, voltage scaling disabled, 32
samples average, 200 ksps, 300-Hz input tone
73
Conversion time
Serial conversion, time-to-output, 24-MHz clock
50
Current consumption
Current consumption
Reference voltage
Reference voltage
Reference voltage
Reference voltage
Input Impedance
Internal 4.3-V equivalent reference⁽²⁾
VDD as reference
Equivalent fixed internal reference (input voltage
scaling enabled). For best accuracy, the ADC
conversion should be initiated through the TI-RTOS™
API to include the gain or offset compensation factors
stored in FCFG1.
Fixed internal reference (input voltage scaling
disabled). For best accuracy, the ADC conversion
should be initiated through the TI-RTOS API to include
the gain or offset compensation factors stored in
FCFG1. This value is derived from the scaled value
(4.3 V) as follows: V_ref = 4.3 V × 1408 / 4095
VDD as reference (Also known as RELATIVE) (input
voltage scaling enabled)
VDD as reference (Also known as RELATIVE) (input
voltage scaling disabled)
200 ksps, voltage scaling enabled. Capacitive input,
input impedance depends on sampling frequency and
sampling time
0.66
0.75
4.3 ^{(2) (5)}
1.48
VDD
VDD / 2.82⁽⁵⁾
>1
(1) Using IEEE Std 1241™-2010 for terminology and test methods.
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.
(3) No missing codes. Positive DNL typically varies from +0.3 to +3.5 depending on device, see Figure 5-24.
(4) For a typical example, see Figure 5-25.
(5) Applied voltage must be within absolute maximum ratings (Section 5.1) at all times.
MAX
V_DD
200
UNIT
V
Bits
ksps
LSB
LSB
LSB
LSB
Bits
dB
dB
dB
clock-
cycles
mA
mA
V
V
V
V
MΩ
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Specifications
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