TMS320C6452_13 Datasheet, PDF (159/181 Pages) Texas Instruments – TMS320C6452 Digital Signal Processor

TMS320C6452
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SPRS371F – OCTOBER 2007 – REVISED APRIL 2012
The MDIO module manages the PHY configuration and monitors status. For a list of supported registers
and register fields, see Table 6-84. In 10/100 mode, the GMII_MTXD(7:0) data bus uses only the lower
nibble.
SGMII
The SGMII/SerDes module contains:
• Gigabit differential current mode logic (CML) receiver/transmitters
• An integrated RX/TX PLL to provide the required high-quality/high-speed internal clocks
• Phase-interpolator-based clock/data recovery
• A bandgap reference for transmitter swing settings
• Parallel-to-serial converter
• Serial-to-parallel converter
• Integrated receiver and transmitter termination
• Configuration logic
• 802.3 auto-negotiation functionality (as defined in Clause 37 of the IEEE Specification 802.3)
The SGMII receive interface converts the encoded receive signals from the differential receive input
terminals (SGMII0RXN: SGMII0RXP, SGMII1RXN: SGMII1RXP) into the required GMAC GMII signals.
The SGMII transmit interface converts the GMAC GMII data into the required encoded differential transmit
output terminals (SGMII0TXN: SGMII0TXP, SGMII1TXN: SGMII1TXP). The GMAC does not source the
transmit error signal. Any transmit frame from the GMAC with an error (ie., underrun) will be indicated as
an error by an error CRC.
6.18.3 Peripheral Register Description(s)
Table 6-83 through Table 6-86 list the registers.
HEX ADDRESS RANGE
0x02D0 3000
0x02D0 3004
0x02D0 3008
0x02D0 300C
0x02D0 3010
0x02D0 3014
0x02D0 3018
0x02D0 301C
0x02D0 3020
0x02D0 3024
0x02D0 3028
0x02D0 302C
0x02D0 3030
0x02D0 3034
0x02D0 3038
0x02D0 303C
0x02D0 3040
0x02D0 3044
0x02D0 3048
0x02D0 304C
0x02D0 3050
Table 6-83. Ethernet Switch Registers
REGISTER ACRONYM
CPSW_ID_VER
CPSW_CONTROL
CPSW_SOFT_RESET
CPSW_STAT_PORT_EN
CPSW_PTYPE
P0_MAX_BLKS
P0_BLK_CNT
P0_FLOW_THRESH
P0_PORT_VLAN
P0_TX_PRI_MAP
GMAC0_GAP_THRESH
GMAC0_SA_LO
GMAC0_SA_HI
P1_MAX_BLKS
P1_BLK_CNT
P1_FLOW_THRESH
P1_PORT_VLAN
P1_TX_PRI_MAP
GMAC1_GAP_THRESH
GMAC1_SA_LO
GMAC1_SA_HI
DESCRIPTION
CPSW Identification and Version Register
CPSW Switch Control Register
CPSW Soft Reset Register
CPSW Statistics Port Enable Register
CPSW Transmit Priority Type Register
CPSW Port 0 Maximum FIFO blocks Register
CPSW Port 0 FIFO Block Usage Count Register (read only)
CPSW Port 0 Flow Control Threshold Register
CPSW Port 0 VLAN Register
CPSW Port 0 Tx Header Pri to Switch Pri Mapping Register
CPSW GMAC0 Short Gap Threshold Register
CPSW GMAC0 Source Address Low Register
CPSW GMAC0 Source Address High Register
CPSW Port 1 Maximum FIFO blocks Register
CPSW Port 1 FIFO Block Usage Count Register (read only)
CPSW Port 1 Flow Control Threshold Register
CPSW Port 1 VLAN Register
CPSW Port 1 Tx Header Priority to Switch Pri Mapping
Register
CPSW GMAC1 Short Gap Threshold Register
CPSW GMAC1 Source Address Low Register
CPSW GMAC1 Source Address High Register
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Peripheral Information and Electrical Specifications 159
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