TMS320C6452_13 Datasheet, PDF (1/181 Pages) Texas Instruments – TMS320C6452 Digital Signal Processor

TMS320C6452
www.ti.com
SPRS371F – OCTOBER 2007 – REVISED APRIL 2012
TMS320C6452 Digital Signal Processor
Check for Samples: TMS320C6452
1 Features
1
• High-Performance Digital Media Processor
– 720-MHz, 900-MHz C64x+™ Clock Rates
– 1.39 ns (-720), 1.11 ns (-900) Instruction
Cycle Time
– 5760, 7200 MIPS
– Eight 32-Bit C64x+ Instructions/Cycle
– Fully Software-Compatible With C64x/Debug
– Commercial Temperature Ranges (-720, -900
only)
– Industrial Temperature Ranges (-720, -900
only)
• VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
– 256K-bit (32K-byte) L1P Program RAM/Cache
[Direct Mapped]
– 256K-bit (32K-byte) L1D Data RAM/Cache
[2-Way Set-Associative]
– 1408KB L2 Unified Mapped RAM/Cache
[Flexible Allocation]
• Supports Little Endian Mode Only
• External Memory Interfaces (EMIFs)
– 32-Bit DDR2 SDRAM Memory Controller With
512M-Byte Address Space (1.8-V I/O)
– Asynchronous 16-Bit Wide EMIF (EMIFA)
• Up to 128M-Byte Total Address Reach
• 64M-Byte Address Reach per CE Space
TMS320C64x+™ DSP Core
– Glueless Interface to Asynchronous
– Eight Highly Independent Functional Units
Memories (SRAM, Flash, and EEPROM)
With VelociTI.2 Extensions:
– Synchronous Memories (SBSRAM and ZBT
• Six ALUs (32-/40-Bit), Each Supports
SRAM)
Single 32-bit, Dual 16-bit, or Quad 8-bit
– Supports Interface to Standard Sync Devices
Arithmetic per Clock Cycle
and Custom Logic (FPGA, CPLD, ASICs,
• Two Multipliers Support Four 16 x 16-bit
etc.)
Multiplies (32-bit Results) per Clock Cycle • Enhanced Direct-Memory-Access (EDMA)
or Eight 8 x 8-bit Multiplies (16-Bit
Controller (64 Independent Channels)
Results) per Clock Cycle
• 3-Port Gigabit Ethernet Switch Subsystem
– Load-Store Architecture With Non-Aligned
Support
• Four 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
– 64 32-bit General-Purpose Registers
• One UART (With RTS and CTS Flow Control)
– Instruction Packing Reduces Code Size
• One 4-wire Serial Port Interface (SPI) With Two
– All Instructions Conditional
Chip-Selects
– Additional C64x+™ Enhancements
• Master/Slave Inter-Integrated Circuit (I2C
• Protected Mode Operation
Bus™)
• Exceptions Support for Error Detection
• Two Telecom Serial Interface Ports (TSIP0/1)
and Program Redirection
• Multichannel Audio Serial Port (McASP)
• Hardware Support for Modulo Loop Auto-
– Ten Serializers and SPDIF (DIT) Mode
Focus Module Operation
• 16/32-Bit Host-Port Interface (HPI)
• C64x+ Instruction Set Features
• Advanced Event Triggering (AET) Compatible
– Byte-Addressable (8-/16-/32-/64-bit Data)
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
– 8-bit Overflow Protection
Interconnect (PCI) Master/Slave Interface
– Bit-Field Extract, Set, Clear
Conforms to PCI Specification 2.3
– Normalization, Saturation, Bit-Counting
• VLYNQ™ Interface (FPGA Interface)
– VelociTI.2 Increased Orthogonality
• On-Chip ROM Bootloader
– C64x+ Extensions
• Individual Power-Saving Modes
• Compact 16-bit Instructions
• Flexible PLL Clock Generators
• Additional Instructions to Support
Complex Multiplies
• IEEE-1149.1 (JTAG™) Boundary-Scan-
Compatible
• C64x+ L1/L2 Memory Architecture
• 32 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
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