English
Language : 

TMS320C6452_13 Datasheet, PDF (154/181 Pages) Texas Instruments – TMS320C6452 Digital Signal Processor
◁
TMS320C6452
SPRS371F – OCTOBER 2007 – REVISED APRIL 2012
www.ti.com
6.17.4 2X Mode Timing
The 2X mode timing is illustrated and defined in Table 6-78, Table 6-79, and Figure 6-45. The nominal
frequency for the selected serial data clock (CLK_A or CLK_B) is 16.384 MHz (± 0.1%), 32.768 MHz (±
0.1%), or 65.536 MHz (± 0.1%), depending on the data rate option. The nominal frequency for the
selected frame sync (FS_A or FS_B) is 8 kHz.
Table 6-78. Timing Requirements for TSIP 2X Mode
NO.
MIN
MAX
1
tc(clk)
Cycle time, CLK rising edge to next CLK rising edge
61 (1)
2
tw(clkl)
Pulse duration, CLK low
0.4 tc(clk)
3
tw(clkh)
Pulse duration, CLK high
0.4 tc(clk)
4
tt(clk)
Transition time, CLK high to low or CLK low to high
2
5
tsu(fs-clk)
Setup time, fs valid before rising CLK
5
6
th(clk-fs)
Hold time, fs valid after rising CLK
5
7
tsu(tr-clk)
Setup time, tr valid before rising CLK
5
8
th(clk-tr)
Hold time, tr valid before rising CLK
5
(1) Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 30.5 ns and 15.2 ns, respectively.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Table 6-79. 2x Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
9
td(clkl-tx)
Delay time, CLK low to TX valid
1
TYP
MAX UNIT
12 ns
CLKA/B
FSA/B
TR[n] ts127-3
TX[n] ts127-3
ts127-2
ts127-2
2
1
3
6
5
ts127-1
ts127-1
ts127-0
ts127-0
7
ts000-7
9
ts000-7
8
ts000-6
ts000-6
ts000-5
ts000-5
ts000-4
ts000-4
ts000-3
ts000-3
ts000-2
ts000-2
ts000-1
ts000-1
ts000-0
ts000-0
Figure 6-45. TSIP 2x Timing Diagram
6.17.5 1X Mode Timing
The 1X mode timing is illustrated and defined in Table 6-80, Table 6-81, and Figure 6-46. The nominal
frequency for the selected serial data clock (CLK_A or CLK_B) is 8.192 MHz (± 0.1%), 16.384 MHz (±
0.1%), or 32.768 MHz (± 0.1%), depending on the data rate option. The nominal frequency for the
selected frame sync (FS_A or FS_B) is 8 kHz.
Table 6-80. Timing Requirements for TSIP 1X Mode
NO.
MIN
MAX
11
tc(clk)
Cycle time, CLK rising edge to next CLK rising edge
122.1 (1)
12
tw(clkl)
Pulse duration, CLK low
0.4 tc(clk)
13
tw(clkh)
Pulse duration, CLK high
0.4 tc(clk)
14
tt(clk)
Transition time, CLK high to low or CLK low to high
2
15
tsu(fs-clk)
Setup time, fs valid before rising CLK
5
16
th(clk-fs)
Hold time, fs valid after rising CLK
5
17
tsu(tr-clk)
Setup time, tr valid before falling CLK
5
18
th(clk-tr)
Hold time, tr valid before falling CLK
5
(1) Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
154 Peripheral Information and Electrical Specifications
Copyright © 2007–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320C6452
 ▷