TMS320C6452_13 Datasheet, PDF (110/181 Pages) Texas Instruments – TMS320C6452 Digital Signal Processor

TMS320C6452
SPRS371F – OCTOBER 2007 – REVISED APRIL 2012
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6.10 External Memory Interface A (EMIFA)
The EMIFA can interface to a variety of external devices or ASICs, including:
• Pipelined and flow-through synchronous-burst SRAM (SBSRAM)
• ZBT (zero bus turnaround) SRAM and late write SRAM
• Synchronous FIFOs
• Asynchronous memory, including SRAM, ROM, and Flash
6.10.1 EMIFA Device-Specific Information
Timing analysis must be done to verify all ac timing requirements are met. TI recommends utilizing I/O
buffer information specification (IBIS) to analyze all ac timing.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS
Models for Timing Analysis Application Report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIFA output signal
lines.
A race condition may exist when certain masters write data to the EMIFA. For example, if master A
passes a software message via a buffer in external memory and does not wait for indication that the write
completes, when master B attempts to read the software message, then the master B read may bypass
the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete
before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
hardware specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the EMIFA module ID and revision register.
3. Perform a dummy read to the EMIFA module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
6.10.2 EMIFA Peripheral Register Description(s)
For more information on the EMIF registers shown in Table 6-41, see TMS320C6452 DSP External
Memory Interface (EMIF) User's Guide (literature number SPRUFF8).
HEX ADDRESS RANGE
0x7000 0000
0x7000 0004
0x7000 0008
0x7000 000C - 0x7000 001C
0x7000 0020
0x7000 0024 - 0x7000 004C
0x7000 0050 - 0x7000 007C
0x7000 0080
0x7000 0084
0x7000 0088
0x7000 008C
0x7000 0090 - 0x7000 009C
0x7000 00A0
Table 6-41. EMIFA Registers
ACRONYM
MIDR
STAT
-
-
BPRIO
-
-
CE2CFG
CE3CFG
-
-
-
AWCC
REGISTER NAME
Module ID and Revision Register
Status Register
Reserved
Reserved
Burst Priority Register
Reserved
Reserved
EMIFA CE2 Configuration Register
EMIFA CE3 Configuration Register
Reserved
Reserved
Reserved
EMIFA Async Wait Cycle Configuration Register
110 Peripheral Information and Electrical Specifications
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