SM72501 Datasheet, PDF (15/28 Pages) National Semiconductor (TI) – SolarMagic Precision, CMOS Input, RRIO, Wide Supply Range Amplifier

SM72501
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SNIS157C – JANUARY 2011 – REVISED APRIL 2013
R₁
+
V_IN
C_IN
-
C_F
R₂
-
+
+
V_OUT
-
V_OUT
R₂
A_V = - _VIN = - _R1
Figure 42. Compensating for Input Capacitance
For the time being, ignore C_F. The AC gain of the circuit in Figure 42 can be calculated as follows:
V_OUT
-R₂/R₁
(s) =
V_IN
s
s²
1
+
§
¨
A₀
R₁
©^R1 ^{+ R}2
+ _{§ A0}
¨©_{CIN R2}
(1)
This equation is rearranged to find the location of the two poles:
2
-1
P_1,2 = _2CIN
1
1
+
r
R₁ R₂
§
¨©
1
R₁
+
1
R₂
4 A₀C_IN
-
R₂
(2)
As shown in Equation 2, as values of R₁ and R₂ are increased, the magnitude of the poles is reduced, which in
turn decreases the bandwidth of the amplifier. Whenever possible, it is best to choose smaller feedback resistors.
Figure 43 shows the effect of the feedback resistor on the bandwidth of the SM72501.
2
V_S = 5V
0
C_F = 0 pF
A_V = -1
-2
R₁ = R₂ = 100 k:
-4
R₁ = R₂ = 30 k:
-6
R₁ = R₂ = 10 k:
-8
R₁ = R₂ = 1 k:
-10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 43. Closed Loop Gain vs. Frequency
Equation 2 has two poles. In most cases, it is the presence of pairs of poles that causes gain peaking. In order to
eliminate this effect, the poles should be placed in Butterworth position, since poles in Butterworth position do not
cause gain peaking. To achieve a Butterworth pair, the quantity under the square root in Equation 2 should be
set to equal −1. Using this fact and the relation between R₁ and R₂, R₂ = −A_V R₁, the optimum value for R₁ can
be found. This is shown in Equation 3. If R₁ is chosen to be larger than this optimum value, gain peaking will
occur.
R₁
<
(1 - A_V)²
2A₀A_VC_IN
(3)
In Figure 42, C_F is added to compensate for input capacitance and to increase stability. Additionally, C_F reduces
or eliminates the gain peaking that can be caused by having a larger feedback resistor. Figure 44 shows how C_F
reduces gain peaking.
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