LMH7324_14 Datasheet, PDF (15/30 Pages) Texas Instruments – Quad 700 ps High Speed Comparator with RSPECL Outputs

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LMH7324
SNOSAZ2F – SEPTEMBER 2007 – REVISED JULY 2010
5V
+
2.5V
+
+
50:
-
Signal Source
50:
V_CCI
V_CCO
IN+
¼
IN- LMH7324
Q Levels:
V_OH = 1.4V
Q ^VOL ^{= 1.0V}
50:
V_EE
V_EE
-5V
+
Figure 19. ANALOG TO LVDS
STANDARD COMPARATOR SETUP
Figure 20 shows a standard comparator setup which creates RSPECL levels because the V_CCO supply voltage is
+5V. In this setup the V_EE pin is connected to the ground level. The V_CCI pin is connected to the V_CCO pin
because there is no need to use different positive supply voltages. The input signal is AC coupled to the positive
input. To maintain reliable results, even for signals with larger amplitudes, the input pins IN+ and IN− are biased
at 1.4V through a resistive divider using a resistor of 1 kΩ to ground and a resistor of 2.5 kΩ to the V_CC and by
adding two decoupling capacitors. Both inputs are connected to the bias level by the use of a 10 kΩ resistor.
With this input configuration the input stage can work in a linear area with signals of approximately 3 V_PP. (See
input level restrictions in the data tables.)
V_IN
10 k:
5V
+
2.5 k:
V_CCI
V_CCO
IN+
¼
IN- LMH7324
Q _Levels:
V_OH = 3.9V
Q ^{VOL = 3.5V}
10 k:
V_REF
+
1 k:
V_EE
V_EE
Figure 20. Standard Setup
DELAY AND DISPERSION
Comparators are widely used to connect the analog world to the digital one. The accuracy of a comparator is
dictated by its DC properties, such as offset voltage and hysteresis, and by its timing aspects, such as rise and
fall times and delay. For low frequency applications most comparators are much faster than the analog input
signals they handle. The timing aspects are less important here than the accuracy of the input switching levels.
The higher the frequencies, the more important the timing properties of the comparator become, because the
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