LMH7324_14 Datasheet, PDF (10/30 Pages) Texas Instruments – Quad 700 ps High Speed Comparator with RSPECL Outputs

LMH7324
SNOSAZ2F – SEPTEMBER 2007 – REVISED JULY 2010
V_CCO
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Output Q
Output Q
V_EE
Figure 14. Equivalent Output Circuitry
The output voltages for ‘1’ and ‘0’ have a difference of approximately 400 mV and are respectively 1.1V (for the
‘1’) and 1.5V (for the ‘0’) below the V_CCO. This swing of 400 mV is enough to drive any LVDS input but can also
be used to drive any ECL or PECL input, when the right supply voltage is chosen, especially the right level for
the V_CCO.
DEFINITIONS
This table provides a short description of the parameters used in the datasheet and in the timing diagram of
Figure 15.
Symbol
I_B
I_OS
TC I_OS
V_OS
TC V_OS
V_RI
V_RID
CMRR
PSRR
A_V
Hyst
V_OH
V_OL
V_OD
I_VCCI
I_VCCO
I_VEE
TR
PW
Text
Input Bias Current
Input Offset Current
Average Input Offset Current Drift
Input Offset Voltage
Average Input Offset Voltage Drift
Input Voltage Range
Input Differential Voltage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Active Gain
Hysteresis
Output Voltage High
Output Voltage Low
Average of V_ODH and V_ODL
Supply Current Input Stage
Supply Current Output Stage
Supply Current V_EE Pin
Maximum Toggle Rate
Pulse Width
Description
Current flowing in or out of the input pins, when both are biased at the V_CM
voltage as specified in the tables.
Difference between the input bias current of the inverting and non-inverting
inputs.
Temperature coefficient of I_OS.
Voltage difference needed between IN+ and IN− to make the outputs change
state, averaged for H to L and L to H transitions.
Temperature coefficient of V_OS.
Voltage which can be applied to the input pin maintaining normal operation.
Differential voltage between positive and negative input at which the input clamp
is not working. The difference can be as high as the supply voltage but excessive
input currents are flowing through the clamp diodes and protection resistors.
Ratio of input offset voltage change and input common mode voltage change.
Ratio of input offset voltage change and supply voltage change from V_S-MIN to V_S-
MAX^.
Overall gain of the circuit.
Difference between the switching point ‘0’ to ‘1’ and vice versa.
High state single ended output voltage (Q or Q). (See Figure 29)
Low state single ended output voltage (Q or Q). (See Figure 29)
(V_ODH + V_ODL)/2
Supply current into the input stage.
Supply current into the output stage while current through the load resistors is
excluded.
Current flowing out of the negative supply pin.
Maximum frequency at which the outputs can toggle at 50% of the nominal V_OH
and V_OL.
Time from 50% of the rising edge of a signal to 50% of the falling edge.
10
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