LMH7324_14 Datasheet, PDF (14/30 Pages) Texas Instruments – Quad 700 ps High Speed Comparator with RSPECL Outputs

LMH7324
SNOSAZ2F – SEPTEMBER 2007 – REVISED JULY 2010
www.ti.com
5V
+
ECL Driver
V_CCI
V_CCO
Coupled
Line Termination
Transmission Line
IN+
¼
IN- ^LMH7324
Q _{RS-PECL Output}
V_OH = 3.9V
Q ^{VOL = 3.5V}
V_EE
V_EE
-5.2V
+
Figure 17. ECL TO RSPECL
Interface from PECL to (RS) ECL
This setup needs the V_CCI pin at +5V because the input logic levels are positive. To obtain the ECL levels at the
output it is necessary to connect the V_CCO to the ground while the V_EE has to be connected to the −5.2V. The
reason for this is that the minimum requirement for the supply is 5V. The high level of the output of the LMH7324
is normally 1.1V below the V_CCO supply voltage, and the low level is 1.5V below this supply. The output levels
are now −1100 mV for the logic ‘1’ and −1500 mV for the logic ‘0’. (See Figure 18.)
5V
+
PECL Driver _Coupled
Transmission Line
PECL levels:
V_OH = 3.9V
V_OL = 3.5V
Line Termination
IN+
IN-
V_CCI
V_CCO
¼
Q
LMH7324
Q
V_EE
V_EE
RSECL Levels:
V_OH = -1100 mV
V_OL = -1500 mV
-5.2V
+
Figure 18. PECL TO RSECL
Interface from Analog to LVDS
As seen in Figure 19, the LMH7324 can be configured to create LVDS levels. This is done by connecting the
V_CCO to 2.5V. As discussed before, the output levels are now at V_CCO −1.1V for the logic ‘1’ and at V_CCO -1.5V for
the logic ‘0’. These levels of 1000 mV and 1400 mV comply with the LVDS levels. As can be seen in this setup,
an AC coupled signal via a transmission line is used. This signal is terminated with 50Ω to the ground. The input
stage has its supply from +5V to −5V, which means that the input common mode level is midway between the
input stage supply voltages.
14
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