LMH7324_14 Datasheet, PDF (13/30 Pages) Texas Instruments – Quad 700 ps High Speed Comparator with RSPECL Outputs

LMH7324
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SNOSAZ2F – SEPTEMBER 2007 – REVISED JULY 2010
PIN DESCRIPTIONS (continued)
Pin Name
Description
32. V_CCI
Positive Supply for Input Stage
33. DAP
Central Pad at the Bottom of the
Package
Part
Comment
A
This supply pin is independent of the supply for the output stage. V_CCI
and V_CCO share the same ground pin V_EE.
All The purpose of this pad is to transfer heat outside the part.
TIPS & TRICKS USING THE LMH7324
This section discusses several aspects concerning special applications using the LMH7324.Topics include the
connection of the DAP in conjunction to the V_EE pins and the use of this part as an interface between several
logic families. Other sections discuss several widely used definitions and terms for comparators. The final
sections explain some aspects of transmission lines and the choice for the most suitable components handling
very fast pulses.
THE DAP AND THE V_EE PINS
To protect the device against damage during handling and production, two antiparallel connected diodes are
placed between the V_EE pins. Under normal operating conditions (all V_EE pins have the same voltage level) these
diodes are not functioning, as can be seen in Figure 16.
The DAP (Die Attach Paddle) functions as a heat sink which means that heat can be transferred, using vias
below this pad, to any appropriate copper plane. The DAP is isolated from all other electrical connections and
therefore it is possible to connect this pad to any voltage within the allowed voltage range of the part. Using a
DAP connection it is common practice to connect such a pad to the lowest supply voltage. However in high
frequency designs it can be useful to connect this pad to another supply such as e.g. the ground plane, while the
V_EE is for example -5 Volt.
A
V_EE
D
DAP
B
V_EE
C
Figure 16. DAP and V_EE Configuration
INTERFACE BETWEEN LOGIC FAMILIES
The LMH7324 can be used to interface between different logic families. The feature that facilitates this is the fact
that the input stage and the output stage use different positive power supply pins which can be used at different
voltages. The only restriction is that both input (V_CCI) and output (V_CCO) supplies require a minimum of 5V
difference relative to V_EE. The negative supply pins are connected together for all four parts. Using the power
pins at different supply voltages enables level-translation between two logic families. For example, it is possible
to translate from logic at negative voltage levels , such as ECL, to logic at positive levels, such as RSPECL and
LVDS and vice versa.
Interface from ECL to RSPECL
The supply pin V_CCI can be connected to ground because the input levels are negative and V_EE is at −5.2V. With
this setup the minimum requirements for the supply voltage of 5V are obtained. The V_CCO pin must operate at
+5V to create the RSPECL levels. (See Figure 17.)
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