LMH7322_14 Datasheet, PDF (14/33 Pages) Texas Instruments – Dual 700 ps High Speed Comparator with RSPECL Outputs

LMH7322
SNOSAU8H – MARCH 2007 – REVISED MAY 2011
Symbol
t_hLE
t_PD-LE
Text
Latch Hold Time
Latch to Output Delay Time
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Table 1. Definitions (continued)
Description
Time the input signal has to remain stable after enabling the latch functionality.
Delay time between the moment the latch input crosses the switching level H to L
and the moment the differential output signal crosses the 50% level.
Note: input signal is opposite to output signal when latch becomes enabled.
Differential
Input Signal
Output Q
Output Q
Differential
Output Signal
PW
't_PDLH
t_PDH
V_overdrive
't_PDHL
t_PDL
80% or 90%
10% or 20%
t_PDH
t_f
t_r
t_PDL
t_PDHd
t_rd
80% or 90%
t_{PDLd 10% or 20%}
t_fd
Figure 19. Timing Definitions
0
t_PDLH = (t_PDH + t_PDL)/ 2
t_PDHL = (t_PDL + t_PDH)/ 2
t_PD = (t_PDLH + t_PDHL)/ 2
V_O ^{'tPDLH = | tPDH - tPDL |}
't_PDHL = | t_PDL - t_PDH |
V_O ^{'tPD = 'tPDLH + 'tPDHL)/ 2}
't_PDQ = | t_PDH - t_PDL |
't_PDQ = | t_PDL - t_PDH |
0
t_PDd = (t_PDHd + t_PDLd)/ 2
't_PDd = | t_PDHd - t_PDLd |
Diff input
t_{h LE}
LE
Q output
t_{PD LE}
t_PDHL
t_{s LE}
Figure 20. LE Timing
Pin
Name
1.
VCCOA
2.
LEA
3.
LEA
4.
VEEA
5.
VCCIA
6.
RHYSA
7.
INA-
Table 2. PIN DESCRIPTIONS
Description
Positive Supply Output Stage
part A
Latch Enable Input
part A
Latch Enable Input Not
Negative Supply
part A
part A
Positive Supply for Input Stage part A
Hysteresis Resistor
part A
Negative Input
part A
Comment
The supply pin for the output stage is independent of the supply pin for
the input pin. This allows output levels of different logic families.
Logic ‘1’ sets the part on hold. Logic levels are RSPECL (Reduced
Swing PECL) compatible.
Logic ‘0’ sets the part on hold. Logic levels are RSPECL compatible.
The supply pin for the negative supply is connected to the VEEB via a
string of two anti-parallel diodes (see Figure 17)
The supply pin for the input stage is independent of the supply for the
output stage.
The hysteresis voltage is determined by connecting a resistor from this
pin to RHREFA.
Input for analog voltages between 200 mV below VEEA and 2V below
VCCIA.
14
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