LMH7322_14 Datasheet, PDF (12/33 Pages) Texas Instruments – Dual 700 ps High Speed Comparator with RSPECL Outputs

LMH7322
SNOSAU8H – MARCH 2007 – REVISED MAY 2011
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The output stage of the LMH7322 is built using two emitter followers, which are referenced to the V_CCO (see
Figure 18.) Each of the output transistors is active when a current is flowing through any external output resistor
connected to a lower supply rail. The output structure is actually the same as for all other ECL devices. Activating
the outputs is done by connecting the emitters to a termination voltage which lies 2V below the V_CCO. In this case
a termination resistor of 50Ω can be used and a transmission line of 50Ω can be driven. Another method is to
connect the emitters through a resistor to the most negative supply by calculating the right value for the emitter
current in accordance with the datasheet tables. Both methods are useful, and it is up to the customer which
method is used. Using 50Ω to the termination voltage means the introduction of an extra supply in the system,
while using resistors to a negative supply means the use of resistors that are much larger than 50Ω and a more
constant output current per stage. The following calculation will show the difference. In this example a V_CCO of
2.5V is used and a V_T of V_CCO-2V and a negative supply of −5V. When connecting the outputs through a 50Ω
resistor to the V_T, the output currents for the high and the low state are respectively 18 mA and 10 mA.
Connecting the outputs through a 400Ω resistor to the −5V supply the output currents for the high and the low
state are respectively 16 mA and 15 mA. Higher resistor values to the V_EE will further reduce power consumption
but will cause a slower transition of the output stage. In the case that this will not harm your application it is a
useful method to reduce power consumption.
VCCO
Output Q
Output Q
VEE
Figure 18. Equivalent Output Circuitry
The output voltages for ‘1’ and ‘0’ have a difference of approximately 400 mV and are respectively 1.1V (for the
‘1’) and 1.5V (for the ‘0’) below the V_CCO. This swing of 400 mV is enough to drive any LVDS input but can also
be used to drive any ECL or PECL input, when the right supply voltage is chosen, especially the right level for
the V_CCO.
Symbol
I_B
I_OS
TC I_OS
V_OS
TC V_OS
V_RI
V_RID
Text
Input Bias Current
Input Offset Current
Average Input Offset Current Drift
Input Offset Voltage
Average Input Offset Voltage Drift
Input Voltage Range
Input Differential Voltage Range
CMRR
PSRR
A_V
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Active Gain
Table 1. Definitions
Description
Current flowing in or out of the input pins, when both are biased at the V_CM
voltage as specified in the tables.
Difference between the input bias current of the inverting and non-inverting
inputs.
Temperature coefficient of I_OS.
Voltage difference needed between IN+ and IN- to make the outputs change
state, averaged for H to L and L to H transitions.
Temperature coefficient of V_OS .
Voltage which can be applied to the input pin maintaining normal operation.
Differential voltage between positive and negative input at which the input clamp
is not working. The difference can be as high as the supply voltage but excessive
input currents are flowing through the clamp diodes and protection resistors.
Ratio of input offset voltage change and input common mode voltage change.
Ratio of input offset voltage change and supply voltage change from V_S-MIN to V_S-
MAX^.
Overall gain of the circuit.
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