LMH7322_14 Datasheet, PDF (13/33 Pages) Texas Instruments – Dual 700 ps High Speed Comparator with RSPECL Outputs

LMH7322
www.ti.com
SNOSAU8H – MARCH 2007 – REVISED MAY 2011
Table 1. Definitions (continued)
Symbol
Text
Description
Hyst
Hysteresis
Difference between the switching point ‘0’ to ‘1’ and vice versa.
I_B-LE
Latch Enable Bias Current
Current flowing in or out of the input pins, when both are biased at normal PECL
levels.
I_OS-LE
TC I_OS-LE
Latch Enable Offset Current
Temp Coefficient Latch Enable Offset
Current
Difference between the input bias current of the LE and LE pin.
Temperature coefficient of I_OS-LE.
V_OS-LE
Latch Enable Offset Voltage
Voltage difference needed between LE and LE to place the part in the latched or
the transparent state.
TC V_OS-LE
Temp Coefficient Latch Enable Offset
Voltage
Temperature coefficient of V_OS-LE.
V_RI-LE
V_RID-LE
Latch Enable Voltage Range
Voltage which can be applied to the LE input pins without damaging the device.
Latch Enable Differential Voltage Range Differential Voltage between LE and LE at which the clamp isn’t working. The
difference can be as high as the supply voltage but excessive input currents are
flowing through the clamp diodes and protection resistors.
V_OH
V_OL
V_OD
I_VCCI
I_VCCO
Output Voltage High
Output Voltage Low
average of V_ODH and V_ODL
Supply Current Input Stage
Supply Current Output Stage
High state single ended output voltage (Q or Q) (see Figure 34).
Low state single ended output voltage (Q or Q) (see Figure 34).
(V_ODH + V_ODL)/2.
Supply current into the input stage.
Supply current into the output stage while current through the load resistors is
excluded.
I_VEE
Supply Current V_EE pin
TR
Maximum Toggle Rate
PW
Pulse Width
Current flowing to the negative supply pin.
Maximum frequency at which the outputs can toggle between the nominal V_OH
and V_OL.
Time from 50% of the rising edge of a signal to 50% of the falling edge.
t_PDH resp t_PDL Propagation Delay
t_PDL resp t_PDH
t_PDLH
t_PDHL
t_PD
t_PDHd resp
t_PDLd
t_OD-disp
t_SR-disp
t_CM-disp
Δt_PDLH resp
Δt_PDHL
Input Overdrive Dispersion
Input Slew Rate Dispersion
Input Common Mode Dispersion
Q to Q Time Skew
Δt_PD
ΔtP_Dd
t_r / t_rd
Average Q to Q Time Skew
Average Diff. Time Skew
Output Rise Time (20% - 80%)
Delay time between the moment the input signal crosses the switching level L to
H and the moment the output signal crosses 50% of the rising edge of Q output
(t_PDH), or delay time between the moment the input signal crosses the switching
level H to L and the moment the output signal crosses 50% of the falling edge of
Q output (t_PDL).
Delay time between the moment the input signal crosses the switching level L to
H and the moment the output signal crosses 50% of the falling edge of Q output
(t_PDL), or delay time between the moment the input signal crosses the switching
level H to L and the moment the output signal crosses 50% of the rising edge of
Q output (t_PDH).
Average of t_PDH and t_PDL.
Average of t_PDL and t_PDH.
Average of t_PDLH and t_PDHL.
Delay time between the moment the input signal crosses the switching level L to
H and the zero crossing of the rising edge of the differential output signal (t_PDHd),
or delay time between the moment the input signal crosses the switching level H
to L and the zero crossing of the falling edge of the differential output signal
(t_PDLd).
Change in t_PD for different overdrive voltages at the input pins.
Change in t_PD for different slew rates at the input pins.
Change in t_PD for different common mode voltages at the input pins.
Time skew between 50% levels of the rising edge of Q output and the falling
edge of output (Δt_PDLH), or time skew between 50% levels of falling edge of Q
output and rising edge of Q output (Δt_PDHL).
Average of t_PDLH and t_PDHL for L to H and H to L transients.
Average of t_PDHd and t_PDLd for L to H and H to L transients.
Time needed for the (single ended or differential) output voltage to change from
20% of its nominal value to 80%.
t_f / t_fd
Output Fall Time (20% - 80%)
Time needed for the (single ended or differential) output voltage to change from
80% of its nominal value to 20%.
t_sLE
Latch Setup Time
Time the input signal has to be stable before enabling the latch functionality.
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