BQ40Z60_16 Datasheet, PDF (13/47 Pages) Texas Instruments – Programmable Battery Management Unit

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bq40z60
SLUSAW3C – DECEMBER 2014 – REVISED JULY 2015
Current Protection Thresholds (continued)
Typical values stated where T_A = 25°C and VCC = 10.8 V, Min/Max values stated where T_A = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
ΔV_SCC
SCC detection
threshold voltage
program step
V_SCC = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 1
V_SCC = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 0
22.2
mV
11.1
V_SCD1
SCD1 detection
threshold voltage
range
V_SCD1 = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 1
V_SCD1 = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 0
–44.4
–22.2
–200
mV
–100
SCD1 detection
V_SCD1 = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 1
–22.2
ΔV_SCD1
threshold voltage
program step
V_SCD1 = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 0
–11.1
mV
V_SCD2
SCD2 detection
threshold voltage
range
V_SCD2 = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 1
V_SCD2 = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 0
–44.4
–22.2
–200
mV
–100
SCD2 detection
V_SCD2 = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 1
–22.2
ΔV_SCD2
threshold voltage
program step
V_SCD2 = V_SRP – V_SRN, PROTECTION_CONTROL[RSNS] = 0
–11.1
mV
V_OFFSET
OCD, SCC, and
SCDx offset error
Post-trim
–2.5
2.5 mV
V_SCALE
OCD, SCC, and
SCDx scale error
No trim
Post-trim
–10%
–5%
10%
5%
8.29 N-CH FET Drive (CHG, DSG)
Typical values stated where T_A = 25°C and VCC = 10.8 V, Min/Max values stated where T_A = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Ratio_DSG = (V_DSG – V_BAT)/V_BAT, 2.2 V < V_BAT <
4.07 V, 10 MΩ between HSRN and DSG
2.133 2.333 2.533
Output voltage ratio
Ratio_CHG = (V_CHG – V_BAT)/V_BAT, 2.2 V < V_BAT <
4.07 V, 10 MΩ between BAT and CHG
2.133 2.333 2.533 —
Ratio_ACFET = (V_ACFET – V_BAT)/V_BAT, 2.2 V < V_BAT
< 4.07 V, 10 MΩ between ACP and ACFET
2.133 2.333 2.533
V_(FETON)
Output voltage, CHG and
DSG on
V_DSG(ON) = V_DSG – V_BAT, V_BAT ≥ 4.07 V, 10 MΩ
between V_HSRN and DSG, V_BAT = 18 V
V_CHG(ON) = V_CHG – V_BAT, V_BAT ≥ 4.07 V, 10 MΩ
between BAT and CHG, V_BAT = 18 V
9.0
9.5
9.0
9.5
10
10 V
ACFET
V_ACFET(ON) = V_ACFET – V_BAT, V_BAT ≥ 4.07 V, 10
MΩ between ACP and ACFET, V_BAT = 18 V
9.0
9.5
10
V_(FETOFF)
Output voltage, CHG and
DSG off
V_DSG(OFF) = V_DSG – V_ACP, 10 MΩ between HSRN
and DSG
V_CHG(OFF) = V_CHG – V_BAT, 10 MΩ between BAT
and CHG
–0.4
–0.4
0.4
0.4 V
ACFET
V_ACFET(OFF) = V_ACFET – V_ACP, V_BAT ≥ 4.07 V, 10
MΩ between ACP and ACFET, V_BAT = 18 V
–0.4
0.4
V_DSG from 0% to 35% V_DSG(ON)(TYP), V_ACP ≥ 2.2 V,
C_L = 4.7 nF between DSG and V_HSRN, 5.1 kΩ
between DSG and C_L, 10 MΩ between V_HSRN and
DSG
200
500
t_R
Rise time
V_CHG from 0% to 35% V_CHG(ON)(TYP), V_ACP ≥ 2.2
V, C_L = 4.7 nF between CHG and BAT, 5.1 kΩ
between CHG and C_L, 10 MΩ between BAT and
CHG
200
500 µs
V_ACFET from 0% to 35% V_{ACFET(ON)(TYP)}, V_ACP ≥
2.2 V, C_L = 4.7 nF between ACFET and ACP, 5.1
kΩ between CHG and C_L, 10 MΩ between ACP
and ACFET
200
500
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