MSP430G2332-EP Datasheet, PDF (10/55 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430G2332-EP
SLAS885A – AUGUST 2012 – REVISED OCTOBER 2012
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Address
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
01h
Table 7. Interrupt Enable Register 1 and 2
7
6
5
4
3
2
1
0
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
Address
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
03h
Table 8. Interrupt Flag Register 1 and 2
7
6
5
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on V_CC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-On Reset interrupt flag. Set on V_CC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V_CC power-up.
Set via RST/NMI pin
7
6
5
4
3
2
1
0
10
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