TMS320C6424_08 Datasheet, PDF (99/245 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347B – MARCH 2007 – REVISED NOVEMBER 2007
Table 3-18. PINMUX1 Register Description (continued)
Bit
Field Name
Description
Pins Controlled
7
RSV
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
–
Host Block Pin Select.
If EMAC operation is desired, EMAC must be placed in reset before
programming PINMUX1. HOSTBK or PINMUX0.RMII to select EMAC pins.
Host Block:
VLYNQ_CLOCK/PCICLK/GP[57]
HD0/VLYNQ_SCRUN/AD18/GP[58]
PCIEN = 0 and HOSTBK = 000: GPIO Mode (default if PCIEN = 0).
Pins function as GPIO (GP[83:57]).
HD1/VLYNQ_RXD0/AD16/GP[59]
HD2/VLYNQ_RXD1/AD17/GP[60]
HD3/VLYNQ_RXD2/PCBE2/GP[61]
PCIEN = 0 and HOSTBK = 001: HPI + 1 GPIO Mode.
Pins function as HPI and GPIO (GP[57]).
HD4/VLYNQ_RXD3/PFRAME/GP[62]
HD5/VLYNQ_TXD0/PIRDY/GP[63]
HD6/VLYNQ_TXD1/PTRDY/GP[64]
PCIEN = 0 and HOSTBK = 010: VLYNQ + 17 GPIO Mode.
HD7/VLYNQ_TXD2/PDEVSEL/GP[65]
Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0], HD8/VLYNQ_TXD3/PPERR/GP[66]
VLYNQ_TXD[3:0]), and GP[83:67].
HD9/MCOL/PSTOP/GP[67]
HD10/MCRS/PSERR/GP[68]
PCIEN = 0 and HOSTBK = 011: VLYNQ + MII + MDIO Mode.
HD11/MTXD3/PCBE1/GP[69]
Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0], _{HD12/MTXD2/PPAR/GP[70]}
6:4
HOSTBK VLYNQ_TXD[3:0]), MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,
HD13/MTXD1/AD14/GP[71]
RXCLK, RXD[3:0]), and MDIO (MDIO, MDC).
HD14/MTXD0/AD15/GP[72]
When EMAC(MII) is selected, EMAC(RMII) must not be selected.
HD15/MTXCLK/AD12/GP[73]
PINMUX0.RMII must be set to 0.
HHWIL/MRXDV/AD13/GP[74]
PCIEN = 0 and HOSTBK = 100: MII + MDIO +10 GPIO Mode.
Pins function as MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,
RXCLK, RXD[3:0]), MDIO (MDIO, MDC), and GP[66:57].
When EMAC(MII) is selected, EMAC(RMII) must not be selected.
PINMUX0.RMII must be set to 0.
HCNTL1/MTXEN/AD11/GP[75]
HCNTL0/MRXER/AD10/GP[76]
HR/W/MRXCLK/AD8/GP[77]
HDS2/MRXD0/AD9/GP[78]
HDS1/MRXD1/AD7/GP[79]
HRDY/MRXD2/PCBE0/GP[80]
PCIEN = 1 and HOSTBK = 000: PCI Mode (default if PCIEN = 1).
Pins function as PCI pins: PCICLK, PCBE2, PCBE1, PCBE0, PFRAME,
PIDRDY, PTRDY, PDEVSEL, PPER, PSTOP, PSERR, PPAR, AD[18:5], and
HCS/MDCLK/AD5/GP[81]
HINT/MRXD3/AD6/GP[82]
HAS/MDIO/AD3/GP[83]
AD03.
The combination of PINMUX1 fields PCIEN and
All other PCIEN and HOSTBK combinations reserved.
HOSTBK select the function of these 27 pins.
3:1
RESERVED
Reserved. For proper device operation, the user should only write "0" to this bit
(default).
–
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Device Configurations
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