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TMS320C6424_08 Datasheet, PDF (160/245 Pages) Texas Instruments – Fixed-Point Digital Signal Processor
TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347B – MARCH 2007 – REVISED NOVEMBER 2007
www.ti.com
6.5.9 Reset Electrical Data/Timing
Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD)
resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor.
Table 6-11. Timing Requirements for Reset (see Figure 6-7 and Figure 6-8)
NO.
1
tw(RESET)
4
tsu(CONFIG)
5
th(CONFIG)
Pulse duration, POR low or RESET low
Setup time, boot and configuration pins valid before POR high or RESET
high (2)
Hold time, boot and configuration pins valid after POR high or RESET
high (2)
-4/-4Q/-4S
-5/-5Q/-5S
-6
MIN
12C (1)
MAX
UNIT
ns
12C (1)
ns
0
ns
(1) C = 1/MXI clock frequency in ns. The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET)
requirement.
(2) For the list of boot and configuration pins, see Table 2-7, Boot Terminal Functions.
Table 6-12. Switching Characteristics Over Recommended Operating Conditions During Reset(1)
(see Figure 6-8)
NO.
PARAMETER
2 td(RSTH-RSTOUTH) Delay time, POR high or RESET high to RESETOUT high
3
tw(PAUSE)
Pulse duration, SYSCLKs paused (low) before RESETOUT high
6
td(RSTL-IV)
Delay time, POR low or RESET low to pins invalid
7
td(RSTH-V)
Delay time, POR high or RESET high to pins valid
8
td(RSTOUTH-V)
Delay time, RESETOUT high to pins valid
9
td(RSTOUTH-IV)
Delay time, RESETOUT high to pins invalid
(1) C = 1/CLKIN1 clock frequency in ns.
-4/-4Q/-4S
-5/-5Q/-5S
-6
MIN
MAX
1900C
10C
10C
20
20
0
12C
UNIT
ns
ns
ns
ns
ns
ns
Figure 6-7 shows the Power-Up Timing. Figure 6-8 shows the Warm Reset (RESET) Timing and Max
Reset Timing are identical to Warm Reset Timing, except the boot and configuration pins are not
relatched and the BOOTCFG register retains its previous value latched before the Max Reset were
initiated.
160 Peripheral Information and Electrical Specifications
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