TMS320C6424_08 Datasheet, PDF (12/245 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347B – MARCH 2007 – REVISED NOVEMBER 2007
2 Device Overview
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2.1 Device Characteristics
Table 2-1, provides an overview of the TMS320C6424 DSP. The tables show significant features of the
C6424 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the
package type with pin count.
Table 2-1. Characteristics of the C6424 Processor
HARDWARE FEATURES
DDR2 Memory Controller
Asynchronous EMIF [EMIFA]
EDMA3
Timers
Peripherals
Not all peripherals pins
are available at the same
time (for more detail, see
the Device Configuration
section).
UARTs
I2C
McBSPs
McASP
10/100 Ethernet MAC (EMAC) with
Management Data Input/Output (MDIO)
VLYNQ
General-Purpose Input/Output Port (GPIO)
PWM
HPI (16-bit)
PCI (32-bit), [33-MHz]
Size (Bytes)
On-Chip Memory
Organization
MegaModule Rev ID
CPU ID + CPU Rev ID
JTAG BSDL_ID
CPU Frequency
Cycle Time
Revision ID Register (MM_REVID.[15:0])
(address location: 0x0181 2000)
Control Status Register (CSR.[31:16])
JTAGID register
(address location: 0x01C4 0028)
MHz
ns
Voltage
PLL Options
BGA Package(s)
Process Technology
Core (V)
I/O (V)
MXI/CLKIN frequency multiplier
(15-30 MHz reference)
16 x 16 mm, 0.8 mm pitch
23 x 23 mm, 1.0 mm pitch
m
C6424
(16-/32-bit bus width) [1.8 V I/O]
Asynchronous (8-/16-bit bus width),
RAM, Flash, (NOR or NAND)
1 (64 independent channels, 8 QDMA channels)
2 64-bit General Purpose
(configurable as 2 64-bit or 4 32-bit)
1 64-bit Watch Dog
2 (one with RTS and CTS flow control)
1 (Master/Slave)
2
1 (4 Serializers)
1
1
Up to 111 pins
3 outputs
1
1
240KB RAM, 64KB ROM
32K-Byte (32KB) L1 Program (L1P) RAM/Cache
(Cache up to 32KB)
80KB L1 Data (L1D) RAM/Cache (Cache up to 32KB)
128KB Unified Mapped RAM/Cache (L2)
64KB Boot ROM
See theTMS320C6424/21 Digital Signal Processor
(DSP) [Silicon Revisions 1.1 and 1.0] Silicon Errata
(literature number SPRZ252).
See Section 6.22.1, JTAG ID (JTAGID) Register
Description(s)
400, 500, 600
2.5 ns (-4/-4Q/-4S)
2 ns (-5/-5Q/-5S)
1.67 ns (-6)
1.2 V (-6, -5, -5Q, -5S, -4, -4Q, -4S)
1.05 V (-6 when SYSCLK1 ≤ 400 MHz only)
1.8 V, 3.3 V
x1 (Bypass), x14 to x32
361-Pin BGA (ZWT)
376-Pin BGA (ZDU)
0.09 m
12
Device Overview
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