TMS320C6424_08 Datasheet, PDF (41/245 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6424
Fixed-Point Digital Signal Processor
SPRS347B – MARCH 2007 – REVISED NOVEMBER 2007
Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued)
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
This pin is multiplexed between EMIFA and GPIO.
EM_BA[1]/
GP[5]/(AEM0)
C16 C20
I/O/Z
EM_A[21]/GP[34] D12 C16
I/O/Z
EM_A[20]/PINTA/
GP[44]
C12
C15
I/O/Z
EM_A[19]/PREQ/
GP[45]
B12
C14
I/O/Z
EM_A[18]/PRST/
GP[46]
D11
A14
I/O/Z
EM_A[17]/AD31/
GP[47]
A11
B14
I/O/Z
EM_A[16]/PGNT/
GP[48]
C11
B13
I/O/Z
EM_A[15]/AD29/
GP[49]
B11
C13
I/O/Z
EM_A[14]/AD27/
GP[50]
A10
A13
I/O/Z
EM_A[13]/AD25/
GP[51]
B10
A12
I/O/Z
EM_A[12]/PCBE3/
GP[89]
D10
B12
I/O/Z
EM_A[11]/AD24/
GP[90]
C10
C12
I/O/Z
EM_A[10]/AD23/
GP[91]
A9
B11
I/O/Z
EM_A[9]/PIDSEL/
GP[92]
D9
C11
I/O/Z
EM_A[8]/AD21/
GP[93]
B9
A11
I/O/Z
EM_A[7]/AD22/
GP[94]
C9
C10
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
For EMIFA, this is the Bank Address 1 output EM_BA[1].
When connected to an 8-bit asynchronous memory, this pin is the 2nd
bit of the address.
When connected to a 16-bit asynchronous memory, this pin is the
lowest order bit of the 16-bit word address.
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 21 output
EM_A[21].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 20 output
EM_A[20].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 19 output
EM_A[19].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 18 output
EM_A[18].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 17 output
EM_A[17].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 16 output
EM_A[16].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 15 output
EM_A[15].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 14 output
EM_A[14].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 13 output
EM_A[13].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 12 output
EM_A[12].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 11 output
EM_A[11].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 10 output
EM_A[10].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 9 output EM_A[9].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 8 output EM_A[8].
This pin is multiplexed between EMIFA, PCI, and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is address bit 7 output EM_A[7].
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