AM1808_1004 Datasheet, PDF (90/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
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6.8.1.1 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 6-11.
Module State
Enable
Module Reset
De-asserted
Module
Clock
On
Disable
De-asserted
Off
SyncReset
Asserted
On
SwRstDisable Asserted
Off
Auto Sleep
De-asserted
Off
Auto Wake
De-asserted
Off
Table 6-11. Module States
Module State Definition
A module in the enable state has its module reset de-asserted and it has its clock on.
This is the normal operational state for a given module
A module in the disabled state has its module reset de-asserted and it has its module
clock off. This state is typically used for disabling a module clock to save power. The
device is designed in full static CMOS, so when you stop a module clock, it retains the
module’s state. When the clock is restarted, the module resumes operating from the
stopping point.
A module state in the SyncReset state has its module reset asserted and it has its
clock on. Generally, software is not expected to initiate this state
A module in the SwResetDisable state has its module reset asserted and it has its
clock disabled. After initial power-on, several modules come up in the SwRstDisable
state. Generally, software is not expected to initiate this state
A module in the Auto Sleep state also has its module reset de-asserted and its module
clock disabled, similar to the Disable state. However this is a special state, once a
module is configured in this state by software, it can “automatically” transition to
“Enable” state whenever there is an internal read/write request made to it, and after
servicing the request it will “automatically” transition into the sleep state (with module
reset re de-asserted and module clock disabled), without any software intervention.
The transition from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are fully
operational and moving data.
A module in the Auto Wake state also has its module reset de-asserted and its module
clock disabled, similar to the Disable state. However this is a special state, once a
module is configured in this state by software, it will “automatically” transition to
“Enable” state whenever there is an internal read/write request made to it, and will
remain in the “Enabled” state from then on (with module reset re de-asserted and
module clock on), without any software intervention. The transition from sleep to
enabled state has some cycle latency associated with it. It is not envisioned to use this
mode when peripherals are fully operational and moving data.
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Peripheral Information and Electrical Specifications
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