AM1808_1004 Datasheet, PDF (118/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
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Figure 6-22 shows the topology and routing for the DQS and DQ net class; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
T
E0
A1
T
E1
A1
Figure 6-22. DQS and DQ Routing and Topology
Table 6-35. DQS and DQ Routing Specification
No. Parameter
Min
Typ
Max
Unit
Notes
1 DQS E Skew Length Mismatch
2 Center to center DQS to other DDR2/mDDR trace
spacing
3 DQS/D nominal trace length
4 D to DQS Skew Length Mismatch
5 D to D Skew Length Mismatch
6 Center to center D to other DDR2/mDDR trace
spacing
7 Center to Center D to other D trace spacing
8 DQ/DQS E Skew Length Mismatch
4w ⁽¹⁾
DQLM-50
4w ⁽¹⁾
3w ⁽¹⁾
DQLM
25
DQLM+50
100
100
100
Mils
See Note ⁽²⁾
Mils See Notes ⁽³⁾, ⁽⁴⁾
Mils See Note ⁽⁴⁾
Mils See Note ⁽⁴⁾
See Notes ⁽²⁾, ⁽⁵⁾
See Notes ⁽⁶⁾, ⁽²⁾
Mils See Note ⁽⁴⁾
(1) w = PCB trace width as defined in Table 6-27 .
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) Series terminator, if used, should be located closest to DDR.
(4) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(5) D's from other DQS domains are considered other DDR2/mDDR trace.
(6) DQLM is the longest Manhattan distance of each of the DQS and D net class.
118 Peripheral Information and Electrical Specifications
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