AM1808_1004 Datasheet, PDF (161/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
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SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
Table 6-76. General Timing Requirements for SPI1 Master Modes⁽¹⁾
NO.
PARAMETER
1 t_c(SPC)M
2 t_w(SPCH)M
Cycle Time, SPI1_CLK, All Master Modes
Pulse Width High, SPI1_CLK, All Master
Modes
3 t_w(SPCL)M
Pulse Width Low, SPI1_CLK, All Master
Modes
Polarity = 0, Phase =
0,
to SPI1_CLK rising
4,5 t_{d(SIMO_SPC)M}
Delay, initial data
bit valid on
SPI1_SIMO to
initial edge on
SPI1_CLK ⁽³⁾
Polarity = 0, Phase =
1,
to SPI1_CLK rising
Polarity = 1, Phase =
0,
to SPI1_CLK falling
Polarity = 1, Phase =
1,
to SPI1_CLK falling
Polarity = 0, Phase =
0,
from SPI1_CLK
rising
Polarity = 0, Phase =
1,
Delay, subsequent _{from SPI1_CLK}
bits valid on
falling
5
t_{d(SPC_SIMO)M}
SPI1_SIMO after
transmit edge of
Polarity = 1, Phase =
SPI1_CLK
0,
from SPI1_CLK
falling
Polarity = 1, Phase =
1,
from SPI1_CLK
rising
Polarity = 0, Phase =
0,
from SPI1_CLK
falling
Polarity = 0, Phase =
1,
Output hold time, _{from SPI1_CLK}
SPI1_SIMO valid _rising
6 t_{oh(SPC_SIMO)M} after
receive edge of
Polarity = 1, Phase =
SPI1_CLK
0,
from SPI1_CLK
rising
Polarity = 1, Phase =
1,
from SPI1_CLK
falling
1.3V, 1.2V
MIN
20 ⁽²⁾
MAX
256P
0.5M-1
0.5M-1
5
-0.5M+5
5
-0.5M+5
5
5
5
5
0.5M-3
0.5M-3
0.5M-3
0.5M-3
1.1V
MIN
30 ⁽²⁾
MAX
256P
0.5M-1
0.5M-1
5
-0.5M+5
5
-0.5M+5
5
5
5
5
0.5M-3
0.5M-3
0.5M-3
0.5M-3
1.0V
MIN
40 ⁽²⁾
MAX
256P
0.5M-1
UNIT
ns
ns
0.5M-1
ns
6
-0.5M+6
ns
6
-0.5M+6
6
6
ns
6
6
0.5M-3
0.5M-3
ns
0.5M-3
0.5M-3
(1) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
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Peripheral Information and Electrical Specifications 161
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