AM1808_1004 Datasheet, PDF (206/264 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
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6.24.2 LCD Raster Mode
Table 6-110. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
See Figure 6-60 through Figure 6-64
NO.
PARAMETER
f_{clock(PIXEL_CLK)}
1 t_{c(PIXEL_CLK)}
2 t_{w(PIXEL_CLK_H)}
3 t_{w(PIXEL_CLK_L)}
4 t_{d(LCD_D_V)}
5 t_{d(LCD_D_IV)}
6
t_{d(LCD_AC_ENB_CS_A)}
7
t_{d(LCD_AC_ENB_CS_I)}
8 t_{d(LCD_VSYNC_A)}
9 t_{d(LCD_VSYNC_I)}
10 t_{d(LCD_HSYNC_A)}
11 t_{d(LCD_HSYNC_I)}
Clock frequency, pixel clock
Cycle time, pixel clock
Pulse duration, pixel clock high
Pulse duration, pixel clock low
Delay time, LCD_PCLK high to LCD_D[15:0] valid (write)
Delay time, LCD_PCLK high to LCD_D[15:0] invalid (write)
Delay time, LCD_PCLK low to LCD_AC_ENB_CS high
Delay time, LCD_PCLK low to LCD_AC_ENB_CS high
Delay time, LCD_PCLK low to LCD_VSYNC high
Delay time, LCD_PCLK low to LCD_VSYNC low
Delay time, LCD_PCLK high to LCD_HSYNC high
Delay time, LCD_PCLK high to LCD_HSYNC low
1.3V, 1.2V,
1.1V
MIN MAX
F/2 ⁽¹⁾
26.66
10
10
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
1.0V
MIN MAX
F/2 ⁽¹⁾
33.33
10
10
0
9
0
9
0
9
0
9
0
9
0
9
0
9
0
9
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) F = frequency of LCD_PCLK in ns
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
• Vertical front porch (VFP)
• Vertical sync pulse width (VSW)
• Vertical back porch (VBP)
• Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
• Horizontal front porch (HFP)
• Horizontal sync pulse width (HSW)
• Horizontal back porch (HBP)
• Pixels per panel (PPL)
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
• AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 6-60. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
206 Peripheral Information and Electrical Specifications
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