TLK1221 Datasheet, PDF (9/23 Pages) Texas Instruments – ETHERNET TRANSCEIVER

TLK1221
www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOD = |TxD – TxN|
Rt = 50 Ω
V_(CM)
Transmit common mode voltage
range
Rt = 50 Ω
Receiver input voltage requirement,
VID = |RxP – RxN|
Receiver common mode voltage
range, (RxP + RxN)/2
C_I
Receiver input capacitance
Differential output jitter, random +
t_(TJ)
Serial data total jitter (peak-to-peak) deterministic, PRBS pattern,
R_ω = 125 MHz
t_(DJ)
Serial data deterministic jitter
(peak-to-peak)
Differential output jitter, PRBS
pattern, R_ω = 125 MHz
t_r, t_f
Differential signal rise, fall time (20% R_L = 50 Ω, C_L = 5 pF, see Figure 6
to 80%)
and Figure 8
Serial data jitter tolerance minimum
required eye opening, (per
IEEE-802.3 specification)
Differential input jitter, random +
deterministic, R_ω = 125 MHz
Receiver data acquisition lock time
from power up
Data relock time from loss of
synchronization
t_{d(Tx latency)} Tx latency
t_{d(Rx latency)} Rx latency
See Figure 1
See Figure 5 and Figure 7
SLLS713 – FEBRUARY 2007
MIN
600
1000
200
1000
100
0.25
20
18
TYP
850
1250
1250
MAX
1100
1400
UNIT
mV
mV
1600 mV
2250 mV
2
pF
0.24
UI
0.12
UI
250
ps
UI
500
µs
1024 Bit times
22
UI
24
UI
TX+
t_r
80%
~V
50%
20%
~V
t_f
TX–
t_f
80%
~V
50%
20%
~V
t_r
VOD
80%
20%
~ 1V
0V
~ –1 V
Figure 6. Differential and Common-Mode Output Voltage Definitions
RXP, RXN
RD(0–9)
10-Bit Code
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9
t_{d(Rx latency)}
10-Bit Code
RBC0
Figure 7. Receiver Latency, TBI Normal Mode Shown
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