TLK1221 Datasheet, PDF (10/23 Pages) Texas Instruments – ETHERNET TRANSCEIVER

TLK1221
SLLS713 – FEBRUARY 2007
CL
5 pF
50 W
CL
5 pF
50 W
Figure 8. Transmitter Test Setup
www.ti.com
CLOCK
1.4 V
t_r
t_f
DATA
t_r
80%
50%
20%
t_f
2V
0.8 V
Figure 9. TTL Data I/O Valid Levels for AC Measurement
LVTTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
t_r(RBC)
t_f(RBC)
t_r
t_f
t_su(d1)
t_h(d1)
t_su(d3)
t_h(d3)
PARAMETER
Clock rise time
Clock fall time
Data rise time
Data fall time
Data setup time
(RD0–RD9)
Data hold time (RD0–RD9)
Data setup time
(RD0–RD9)
Data hold time (RD0–RD9)
TEST CONDITIONS
80% to 20% output voltage, C = 5 pF (see
Figure 9)
TBI normal mode (see Figure 3), R_ω = 125 MHz,
data valid prior to RBC0 rising
TBI normal mode (see Figure 3), R_ω= 61.44
MHz, data valid prior to RBC0 rising
TBI normal mode (see Figure 3), R_ω = 125 MHz,
data valid after RBC0 rising
TBI normal mode (see Figure 3), R_ω = 61.44
MHz, data valid after RBC0 rising
TBI half-rate mode, R_ω = 125 MHz (see
Figure 2)
TBI half-rate mode, R_ω = 125 MHz (see
Figure 2)
MIN
TYP
0.3
0.3
0.3
0.3
2.5
5
2
4
2.5
1.5
TRANSMITTER TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
t_su(d4)
t_h(d4)
t_r, t_f
PARAMETER
Data setup time (TD0–TD9)
Data hold time (TD0–TD9)
TD[0,9] data rise and fall time
TEST CONDITIONS
See Figure 9
MIN
TYP
1.6
0.8
MAX
1.5
1.5
1.5
1.5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
2
UNIT
ns
ns
ns
10
Submit Documentation Feedback