TLK1221 Datasheet, PDF (7/23 Pages) Texas Instruments – ETHERNET TRANSCEIVER

TLK1221
www.ti.com
SLLS713 – FEBRUARY 2007
Table 2. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
SYNCEN
32
SYNC/PASS
30
TEST
LOOPEN
15
PRBSEN
31
ENABLE
POWER
VDD
VDDA
VDDPLL
GROUND
GNDA
GNDQFN
1
6, 16, 26
37
36
35, 40
PAD
I/O
I
P/U ⁽²⁾
O
DESCRIPTION
Synchronous function enable. When SYNCEN is high, the internal synchronization function
is activated. When this function is activated, the transceiver detects the comma pattern
(0011 111 negative beginning disparity) in the serial data stream and realigns data on byte
boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9.
Synchronous detect. The SYNC output is asserted high upon detection of the comma
pattern in the serial data path. SYNC pulses are output only when SYNCEN is activated
(asserted high). In PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of
the PRBS test results (high = pass).
I
P/D ⁽³⁾
I
P/D ⁽³⁾
I
P/D ⁽²⁾
Loop enable. When LOOPEN is high (active), the internal loopback path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loopback test. LOOPEN is held low during standard
operational state with external serial outputs and inputs active.
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the
receive inputs and checked for errors, which are reported by the SYNC/PASS terminal
indicating low.
When this terminal is low, the device is disabled for Iddq testing. RD0–RD9, RBCn, TXP and
TXN are high-impedance. The pullup and pulldown resistors on any input are disabled.
When ENABLE is high, the device operates normally.
Supply
Supply
Supply
Digital logic power. Provides power for all digital circuitry and digital I/O buffers
Analog power. VDDA provides power for the high-speed analog circuits, receiver, and
transmitter.
PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
Ground
Ground
Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers
(2) P/U = Internal pullup resistor
(3) P/D = Internal pulldown resistor
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V_DD
V_I
V_I
ESD
T_stg
T_A
Supply voltage⁽²⁾
Input voltage range at TTL terminals
Input voltage range at other terminals
Electrostatic discharge
Storage temperature
Characterized free-air temperature range
VALUE ⁽¹⁾
–0.3 to 3
–0.5 to 4
–0.3 to V_DD + 0.3
CDM: 1, HBM: 2
–65 to 150
–40 to 85
UNIT
V
V
V
kV
°C
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
DISSIPATION RATINGS
PACKAGE
RHA ^{(1) (2)}
T_A ≤ 25°C
POWER RATING
2.85 W
DERATING FACTOR
ABOVE T_A = 25°C
28 mW/°C
T_A = 70°C
POWER RATING
1.57 W
(1) The thermal resistance junction to ambient of the RHA package is 35°C/W measured on a high-K board.
(2) The thermal resistance junction-to-case (exposed pad) of the RHA package is 5°C/W.
T_A = 85°C
POWER RATING
1.4 W
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